摘要:
A test architecture performs calibration and site verification testing of the effectiveness of a radiation shielding structure within which electronic equipment is housed. An external subsystem is outside a shielding cabinet, and an internal subsystem resides with the electronic equipment within the shielded equipment housing proper. The external subsystem includes a host computer, which controls the operation of transmit and receive subsystems. An external receiver is selectively coupled by the host processor to either an RF receive antenna or to a current sense probe. All control signals from the external subsystem are conveyed into the shielded cabinet by way of fiber optic links, in order to preserve the shielding effectiveness of the cabinet. Having the source of test signals and its associated transmission antenna located within the shielded cabinet serves to minimize the impact of such signals on circuits within the environment outside the cabinet.
摘要:
In a first exemplary embodiment of the invention, an externally and photonically energized unit comprises a shaped resonant cavity, with selected material for converting the incident photons into other electromagnetic radiation for resonance within the cavity; and a pick-up element for receiving and applying the resonant electromagnetic radiation to one or more components external to the resonant cavity. In a wideband modulation mode, the resonant cavity contains a modulation element to which a first information signal is applied. When photons, such as from an x-ray burst, traverse the resonant cavity, a wideband RF signal is generated within the resonant cavity which is modulated by the information signal. In further embodiments, the resonant cavities provide local power based on the remotely sourced photonic wave, as well as enhanced detectors.
摘要:
Pulse width modulated (“Class D”) amplifiers and controllers switching in the 50 khz to 2 MHz range generate harmonics which interfere with AM radio reception. This has precluded wide spread acceptance of class D amplifiers in products with an AM radio. The amplifiers described here use a modified modulation technique when operating with an AM radio to avoid generating harmonics at the receiver selected frequency or its intermediate (IF) frequency. One embodiment uses a harmonic avoidance modulator. A second embodiment uses two or more oscillators and tests for the least distorted output signal. A third embodiment switches the mode of operation to a class AB amplifier when an AM signal is amplified.
摘要:
The hybrid antenna includes a spiral antenna, e.g. a log spiral antenna, and a patch array layer adjacent to the spiral antenna and including a passive periodic patch array of conductive patch elements. A conductive ground plane may be adjacent to the patch array layer, and a dielectric layer may be between the conductive ground plane and the patch array. The spiral antenna may include an upper antenna arm, a lower antenna arm and a dielectric sheet therebetween. Each of the upper and lower antenna arms may be a printed planar conductive trace that is wider at a distal end thereof with respect to a center of the log spiral antenna. The patch or periodic array layer operates in conjunction with the ground plane to couple energy into the spiral antenna and thereby improve low frequency antenna efficiency while maintaining electrically small dimensions.
摘要:
Pulse width modulated (“Class D”) amplifiers and controllers switching in the 50 khz to 2 MHz range generate harmonics that interfere with AM radio reception. This interference has precluded wide spread acceptance of class D amplifiers in products that include an AM radio. The amplifier described here uses a a harmonic avoidance modulator when operating with an AM radio to avoid generating harmonics at the receiver selected frequency or the intermediate (IF) frequency thereof.
摘要:
A partitioned constant delay logic network 208 has a number of constant delay logic elements. The delay of each logic element is held constant by applying a controlled bias voltage, V.sub.bias. The source of the controlled bias voltage is a phase locked loop 201 which has a voltage controlled oscillator 203 constructed out of an odd plurality of constant delay logic elements.
摘要:
A low noise logic (LNL) family is disclosed. An inverter 10 has a pair of load devices NL1, NL2 coupled to the drains of NMOS transistors N 1, N2. The input signal is coupled to the gate of N 1. The drain of N 1 is coupled to the gate of N2. A constant current source 12 is coupled between V.sub.ss and the sources of the transistors N1,N2. Trickle current devices NTR1, NTR2 are coupled to the drains of N 1, N2, respectively to insure input control of the output states. A high logic signal on the gate of N1 steers the constant current to the load NL1 and turns NL2 off. A low logic signal on the gate of N1 turns N1 off and applies a high voltage to the gate of N2, turning N2 on. N2 steers the constant current to NL2.