Multiplex digital communication system for transmitting channel
identification information
    3.
    发明授权
    Multiplex digital communication system for transmitting channel identification information 失效
    用于传输信道识别信息的多路数字通信系统

    公开(公告)号:US5400163A

    公开(公告)日:1995-03-21

    申请号:US788454

    申请日:1991-11-06

    摘要: Multiplex communication system for transmitting different signals through a plurality of channels comprises a transmitter and a receiver. The transmitter comprises a transmitting section for multiplexing and transmitting the different signals through the plurality of channels, and an adder for adding channel identification signals for identifying the respective channels to the signals to be transmitted through the respective channels. The receiver comprises a setting device for setting a desired channel, a detector for detecting the channel identification signals from the signals transmitted from the transmitter, and a channel selector for selecting the channel signal preset by the setting device in accordance with the outputs of the setting device and the detector.

    摘要翻译: 用于通过多个信道发送不同信号的多路复用通信系统包括发射机和接收机。 发射机包括用于通过多个信道复用和发送不同信号的发送部分,以及用于将用于识别相应信道的信道识别信号添加到要通过各个信道发送的信号的加法器。 接收机包括用于设置所需信道的设置装置,用于从发射机发送的信号中检测信道识别信号的检测器和用于根据设置的输出来选择由设置装置预设的信道信号的信道选择器 设备和检测器。

    Multiplexer
    4.
    发明授权
    Multiplexer 有权
    复用器

    公开(公告)号:US07340182B2

    公开(公告)日:2008-03-04

    申请号:US10471732

    申请日:2002-03-14

    IPC分类号: H04B10/12

    摘要: A multiplexer includes an encoder. The encoder includes: flip-flop circuits that output two signals having a transmission rate of B/2 at a frequency of B/2, while holding signals of each signal; an adder that adds the respective signals output from the flip-flop circuits and outputs the added signal; and a delay unit that delays the signal output from the flip-flop circuit by the time of 1/B, with respect to the signal output from the flip-flop circuit, and outputs the signal delayed to the adder.

    摘要翻译: 复用器包括编码器。 编码器包括:在保持每个信号的信号的同时,以B / 2的频率输出具有B / 2的传输速率的两个信号的触发器电路; 加法器,其将从触发器电路输出的各个信号相加并输出相加的信号; 以及延迟单元,相对于从触发器电路输出的信号,将从触发器电路输出的信号延迟1 / B的时间,并将延迟的信号输出到加法器。

    Light burst transmission/reception control system, parent station device used in the same, child station device, and light burst transmission/reception control method
    6.
    发明授权
    Light burst transmission/reception control system, parent station device used in the same, child station device, and light burst transmission/reception control method 有权
    光突发发送/接收控制系统,使用的母站设备,子站设备和光突发发送/接收控制方法

    公开(公告)号:US07139487B2

    公开(公告)日:2006-11-21

    申请号:US10049855

    申请日:2001-06-08

    IPC分类号: H04J14/08

    摘要: A host station apparatus (10) generates band allocation information including identifications of slave station apparatuses (20-1 through 200-n) and types of data to be transmitted by the slave station apparatuses and posts the information to the plural slave station apparatuses (20-1 through 20-n). The plural slave station apparatuses (20-1 through 20-n) identify as to whether or not the band allocation information is band allocation information about the data types of the slave station apparatuses respectively, and when the band allocation information is band allocation information about the data types of the slave station apparatuses, they control to transmit data to the host station apparatus (10) according to the data types represented by the band allocation information.

    摘要翻译: 主站装置(10)生成包括从站装置(20-1〜200-n)的标识的频带分配信息和从站发送装置的数据种类,并将该信息发送给多个从站装置(20 1〜20 -n)。 多个从站装置(20-1〜20-n)分别确定频带分配信息是否是关于从站装置的数据类型的频带分配信息,并且当频带分配信息是关于 从属站装置的数据类型,根据由频带分配信息表示的数据类型,控制向主机装置(10)发送数据。

    Data transmission and reception system, data transmitter and data receiver
    8.
    发明授权
    Data transmission and reception system, data transmitter and data receiver 有权
    数据收发系统,数据发射机和数据接收机

    公开(公告)号:US06959011B2

    公开(公告)日:2005-10-25

    申请号:US09734618

    申请日:2000-12-13

    CPC分类号: H04J3/1611 H04J3/0608

    摘要: The data transmission and reception system comprises a data transmitter and a data receiver. The data transmitter generates and transmits a high-speed serial signal through a transmission path and the data receiver receives the serial signal. The data transmitter, when forming the frame for every tributary signal, inserts into the frame a frame bit indicating a boundary of the frame and, after having formed the frame, performs only a bit synchronization with respect to every tributary signal. On the other hand, the data receiver, for a respective tributary signal, stores a data indicated by the tributary signal and, in a timing based on a detection of the frame bit of the tributary signal and a reference frame pulse commonly issued between tributary signals, outputs the stored data to thereby perform the tributary synchronization.

    摘要翻译: 数据发送和接收系统包括数据发送器和数据接收器。 数据发送器通过传输路径产生并发送高速串行信号,数据接收器接收串行信号。 数据发送器在为每个支路信号形成帧时,将表示帧的边界的帧比特插入到帧中,并且在形成帧之后,仅对每个支路信号执行比特同步。 另一方面,对于相应的支路信号,数据接收机存储由辅助信号指示的数据,并且在基于支路信号的帧位的检测的定时以及通常在支路信号之间发出的参考帧脉冲 ,输出所存储的数据,从而执行支路同步。

    Optical transmission system, fec multiplexer, fec multiplexer/separator, and error correction method
    9.
    发明授权
    Optical transmission system, fec multiplexer, fec multiplexer/separator, and error correction method 失效
    光传输系统,fec多路复用器,fec多路复用器/分离器和纠错方法

    公开(公告)号:US07043162B2

    公开(公告)日:2006-05-09

    申请号:US10031235

    申请日:2001-05-16

    IPC分类号: H04B10/00

    摘要: An FEC multiplexing circuit (2) has a configuration in which a first memory circuit (15) is arranged on the input stage of a first RS encoding circuit (16), a second memory circuit (17) is arranged on the input stage of a second RS encoding circuit (18), error correction encoding is performed by a combination of different data having two directions, and thereafter, error correction codes are multiplexed to generate an FEC frame. On the other hand, an FEC demultiplexing circuit (6) has a configuration in which a third memory circuit (42) is arranged on the output stage of a first RS decoding circuit (41), a fourth memory circuit (44) is arranged on the output stage of a second RS decoding circuit (43), error correction is performed by a combination of different data having two directions, and, thereafter, parallel data read from the fourth memory circuit (44) are multiplexed to reproduce original information data.

    摘要翻译: FEC复用电路(2)具有第一存储器电路(15)布置在第一RS编码电路(16)的输入级上的配置,第二存储器电路(17)布置在输入级 第二RS编码电路(18),通过具有两个方向的不同数据的组合来执行纠错编码,然后对纠错码进行多路复用以产生FEC帧。 另一方面,FEC解复用电路(6)具有第三存储电路(42)配置在第一RS解码电路(41)的输出级上的结构,第四存储电路(44)配置在 通过具有两个方向的不同数据的组合来执行第二RS解码电路(43)的输出级,然后对从第四存储器电路(44)读取的并行数据进行多路复用以再现原始信息数据。

    Multiplexing system and multiplexing method of tributary signals
    10.
    发明授权
    Multiplexing system and multiplexing method of tributary signals 失效
    支路信号的复用系统和复用方法

    公开(公告)号:US06870859B1

    公开(公告)日:2005-03-22

    申请号:US09518264

    申请日:2000-03-03

    IPC分类号: H04J3/00 H04J3/04 H04Q11/04

    CPC分类号: H04Q11/0478 H04J2203/0089

    摘要: A multiplex transmission system of tributary signals multiplexes a plurality of tributary signals after adding to them frame information common to all the tributary signals and identification codes different for the individual tributary signals. This makes it possible to solve a problem of a conventional multiplex system of tributary signals in that the transmission rate is limited because it multiplexes a plurality of tributary signals with adding an SOH (section overhead) to generate an STM-N frame to be transmitted and received, which requires a considerable time.

    摘要翻译: 辅助信号的多路复用传输系统在添加了多个辅助信号之后,复用多个辅助信号,所述辅助信号与所有辅助信号共同的帧信息和对于各个辅助信号不同的识别码。 这使得可以解决常规的辅助信号多路复用系统的问题在于传输速率受到限制,因为它将多个辅助信号与SOH(部分开销)相加以产生要发送的STM-N帧,并且 收到,这需要相当长的时间。