公开(公告)号：US20190066814A1

公开(公告)日：2019-02-28

申请号：US15684239

申请日：2017-08-23

Applicant: ARM Limited

Inventor： Rajiv Kumar Sisodia ,  Renu Rawat ,  Paul Darren Hoxey ,  Vikash ,  Kumaraswamy Ramanathan ,  Sanjay Mangal ,  Yew Keong Chong

IPC: G11C29/12 ,  G11C11/418 ,  G11C11/419

CPC classification number: G11C29/1201 ,  G11C5/066 ,  G11C7/1018 ,  G11C7/1036 ,  G11C11/418 ,  G11C11/419 ,  G11C29/12015 ,  G11C29/32 ,  G11C2029/1204 ,  G11C2207/107

Abstract: A circuit includes a bitcell array having a plurality of bitlines, and an I/O functional unit to read data stored in the bitcell array. The I/O functional unit includes a first multiplexer to select a first input port or a first bitline among a first group of bitlines, a first latch to latch the output of the first multiplexer, a second multiplexer to select a second input port or a second bitline among a second group of bitlines. The second input port is coupled to an output port of the first latch. The I/O functional unit further includes a second latch to latch the output of the second multiplexer.

公开(公告)号：US10861575B2

公开(公告)日：2020-12-08

申请号：US16666164

申请日：2019-10-28

Applicant: Arm Limited

Inventor： Rajiv Kumar Sisodia ,  Renu Rawat ,  Paul Darren Hoxey ,  Vikash ,  Kumaraswamy Ramanathan ,  Sanjay Mangal ,  Yew Keong Chong

IPC: G11C29/12 ,  G11C11/418 ,  G11C11/419 ,  G11C7/10 ,  G11C29/32 ,  G11C5/06

Abstract: A circuit includes a bitcell array having a plurality of bitlines, and an I/O functional unit to read data stored in the bitcell array. The I/O functional unit includes a first multiplexer to select a first input port or a first bitline among a first group of bitlines, a first latch to latch the output of the first multiplexer, a second multiplexer to select a second input port or a second bitline among a second group of bitlines. The second input port is coupled to an output port of the first latch. The I/O functional unit further includes a second latch to latch the output of the second multiplexer.

公开(公告)号：US20200066365A1

公开(公告)日：2020-02-27

申请号：US16666164

申请日：2019-10-28

Applicant: Arm Limited

Inventor： Rajiv Kumar Sisodia ,  Renu Rawat ,  Paul Darren Hoxey ,  Vikash ,  Kumaraswamy Ramanathan ,  Sanjay Mangal ,  Yew Keong Chong

IPC: G11C29/12 ,  G11C11/419 ,  G11C11/418 ,  G11C29/32 ,  G11C7/10

Abstract: A circuit includes a bitcell array having a plurality of bitlines, and an I/O functional unit to read data stored in the bitcell array. The I/O functional unit includes a first multiplexer to select a first input port or a first bitline among a first group of bitlines, a first latch to latch the output of the first multiplexer, a second multiplexer to select a second input port or a second bitline among a second group of bitlines. The second input port is coupled to an output port of the first latch. The I/O functional unit further includes a second latch to latch the output of the second multiplexer.

公开(公告)号：US10460822B2

公开(公告)日：2019-10-29

申请号：US15684239

申请日：2017-08-23

Applicant: ARM Limited

Inventor： Rajiv Kumar Sisodia ,  Renu Rawat ,  Paul Darren Hoxey ,  Vikash ,  Kumaraswamy Ramanathan ,  Sanjay Mangal ,  Yew Keong Chong

IPC: G11C29/12 ,  G11C11/418 ,  G11C11/419 ,  G11C7/10 ,  G11C29/32 ,  G11C5/06

Abstract: A circuit includes a bitcell array having a plurality of bitlines, and an I/O functional unit to read data stored in the bitcell array. The I/O functional unit includes a first multiplexer to select a first input port or a first bitline among a first group of bitlines, a first latch to latch the output of the first multiplexer, a second multiplexer to select a second input port or a second bitline among a second group of bitlines. The second input port is coupled to an output port of the first latch. The I/O functional unit further includes a second latch to latch the output of the second multiplexer.