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    Clock Circuitry for Memory Applications
    2.
    发明公开
    Clock Circuitry for Memory Applications 审中-公开

    公开(公告)号：US20240290363A1

    公开(公告)日：2024-08-29

    申请号：US18113438

    申请日：2023-02-23

    Applicant: Arm Limited

    Inventor： Rahul Mathur ,  Sanjay Mangal ,  Hemavathi Chaya ,  Kyung Woo Kim ,  Pratik Ghanshambhai Satasia ,  Edward Martin McCombs

    IPC: G11C7/22 ,  G11C11/418 ,  G11C11/419

    CPC classification number: G11C7/222 ,  G11C11/418 ,  G11C11/419

    Abstract: Various implementations described herein are related to a device with a first clock generator that provides a first pulse signal based on a clock signal, wherein the first clock generator has a first tracking circuit that provides a first reset signal based on the first pulse signal. The device may include a second clock generator that provides a second pulse signal based on the clock signal, wherein the second clock generator has a second tracking circuit that provides a first control signal based on the second pulse signal. Also, the device may include a third clock generator that provides a third pulse signal based on the first reset signal, wherein the third clock generator has a logic circuit that provides a second control signal based on the third pulse signal.

    Level shift latch circuitry
    3.
    发明授权
    Level shift latch circuitry 有权

    公开(公告)号：US11005461B2

    公开(公告)日：2021-05-11

    申请号：US16004009

    申请日：2018-06-08

    Applicant: Arm Limited

    Inventor： Andy Wangkun Chen ,  Sai Sriharsha Manapragada ,  Yicong Li ,  Yew Keong Chong ,  Bikas Maiti ,  Sanjay Mangal ,  Hsin-Yu Chen

    IPC: H03K3/356 ,  H03K17/22

    Abstract: Various implementations described herein are directed to an integrated circuit having first devices arranged to operate as a latch. The first devices may include inner devices and outer devices. The integrated circuit may include second devices coupled to the first devices and arranged to operate as a level shifter. The second devices may include upper devices and lower devices. The lower devices may be cross-coupled to gates of the inner devices and the upper devices. The integrated circuit may include input signals applied to gates of the outer devices and the lower devices to thereby generate output signals from the outputs of the lower devices that are applied to the gates of the inner devices and the upper devices to activate latching of the output signals.

    Memory device and method of controlling leakage current within such a memory device
    6.
    发明授权
    Memory device and method of controlling leakage current within such a memory device 有权
    存储器件和控制这种存储器件内的漏电流的方法

    公开(公告)号：US09147451B2

    公开(公告)日：2015-09-29

    申请号：US13847743

    申请日：2013-03-20

    Applicant: ARM Limited

    Inventor： Yew Keong Chong ,  Sanjay Mangal ,  Hsin-Yu Chen

    IPC: G11C11/00 ,  G11C7/18 ,  G11C16/10 ,  G11C16/24 ,  G11C16/26

    CPC classification number: G11C7/18 ,  G11C16/10 ,  G11C16/24 ,  G11C16/26

    Abstract: A memory device includes an array of memory cells arranged as a plurality of rows and columns, each row being coupled to an associated read word line, and each column forming at least one column group, where the memory cells of each column group are coupled to an associated read bit line. Each column group includes circuitry to precharge the associated read bit line to a first voltage level prior to the read operation. Each memory cell has coupling circuitry connected between the associated read bit line and a second voltage level different to the first voltage level. During read operation the coupling circuitry associated with the activated memory cell selectively discharges the associated read bit line towards the second voltage level dependent on the data value stored within that activated memory cell. The clamping circuitry connects the associated read bit line to the second voltage level.

    Abstract translation: 存储器装置包括布置成多个行和列的存储器单元的阵列，每行耦合到相关联的读取字线，并且每列形成至少一个列组，其中每个列组的存储单元耦合到 相关的读位线。 每列组包括在读取操作之前将相关读取位线预充电到第一电压电平的电路。 每个存储单元具有连接在相关读取位线和不同于第一电压电平的第二电压电平之间的耦合电路。 在读取操作期间，与激活的存储器单元相关联的耦合电路根据存储在该激活的存储器单元内的数据值，选择性地将关联的读取位线朝向第二电压电平放电。 钳位电路将相关读取位线连接到第二电压电平。

    Contention-adapted read-write pulse generation circuitry
    7.
    发明授权
    Contention-adapted read-write pulse generation circuitry 有权

    公开(公告)号：US11501809B1

    公开(公告)日：2022-11-15

    申请号：US17348209

    申请日：2021-06-15

    Applicant: Arm Limited

    Inventor： Sanjay Mangal ,  Bikas Maiti

    IPC: G11C8/14 ,  G11C8/08 ,  G11C7/12 ,  G06F13/16 ,  G11C7/18 ,  G11C7/10

    Abstract: Various implementations described herein refer to a device having an address bus that provides multi-port addresses from multiple ports including a first address from a first port and a second address from a second port. The device may have column contention-detection circuitry that receives the multi-port addresses from the address bus, compares the first address from the first port with the second address from the second port and provides a contention adjustment signal based on the comparison between the first address and the second address. The device may have bitline collision circuitry that receives the contention adjustment signal, senses wire-to-wire variation related to bitline coupling effects and provides a bitline collision signal based on sensing the bitline coupling effects.

    Clock generation circuitry for memory applications
    9.
    发明授权
    Clock generation circuitry for memory applications 有权

    公开(公告)号：US10008260B1

    公开(公告)日：2018-06-26

    申请号：US15490352

    申请日：2017-04-18

    Applicant: ARM Limited

    Inventor： Bikas Maiti ,  Rahul Mathur ,  Sanjay Mangal

    IPC: G11C7/22 ,  G11C11/419

    CPC classification number: G11C11/419 ,  G11C5/14 ,  G11C7/22 ,  G11C7/222

    Abstract: Various implementations described herein are directed to an integrated circuit having level shift circuitry that receives a clock signal in a first voltage domain from a first voltage supply and provides a level shifted clock signal in a second voltage domain based on a second voltage supply that is different than the first voltage supply. The integrated circuit may include clock generator pulse circuitry that receives the clock signal in the first voltage domain from the first voltage supply and receives the level shifted clock signal in the second voltage domain from the level shift circuitry.

    Retention voltages for integrated circuits
    10.
    发明授权
    Retention voltages for integrated circuits 有权

    公开(公告)号：US09620200B1

    公开(公告)日：2017-04-11

    申请号：US15081869

    申请日：2016-03-26

    Applicant: ARM Limited

    Inventor： Sanjay Mangal ,  Gus Yeung ,  Martin Jay Kinkade ,  Rahul Mathur ,  Bal S. Sandhu ,  George McNeil Lattimore

    IPC: G11C11/00 ,  G11C11/419 ,  G11C11/413 ,  G11C11/412 ,  H01L27/11

    CPC classification number: G11C11/419 ,  G11C5/148 ,  G11C11/412 ,  G11C11/413 ,  G11C11/417 ,  H01L27/11 ,  H01L27/1104

    Abstract: Various implementations described herein may be directed to retention voltages for integrated circuits. In one implementation, an integrated circuit may include functional circuitry to store data bits, and may also include retention mode circuitry coupled to the functional circuitry to provide retention voltages to the functional circuitry, where the retention mode circuitry may include a first circuitry to provide a first retention voltage to the functional circuitry. The first circuitry may include a first diode device, and may include a first transistor device, a second diode device, or combinations thereof. The retention mode circuitry may also include a second circuitry to provide a second retention voltage to the functional circuitry, where the second circuitry includes second transistor devices. Further, the functional circuitry may be held in a data retention mode when the first retention voltage or the second retention voltage is provided to the functional circuitry.

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