公开(公告)号：US20220196734A1

公开(公告)日：2022-06-23

申请号：US17127846

申请日：2020-12-18

Applicant: Arm Limited

Inventor： Richard Andrew Paterson ,  Rainer Herberholz ,  Peter Andrew Rees Williams ,  Oded Golombek ,  Einat Luko ,  Jeffrey Scott Boyer

IPC: G01R31/3177 ,  G01R31/317

Abstract: Disclosed are methods, systems and devices for implementing built-in self-test (BIST) to be performed by an untrusted party and/or in an unsecure testing environment. In an embodiment, a test access port (TAP) on a device may enable a party to initiate execution of one or more BIST procedures on the device. Additionally, such a TAP may enable loading of encrypted instructions to be executed by one or more processors formed on a device under test.

公开(公告)号：US11545976B1

公开(公告)日：2023-01-03

申请号：US17393788

申请日：2021-08-04

Applicant: Arm Limited

Inventor： Richard Andrew Paterson ,  Robert John Harrison

IPC: H03K19/00 ,  H03K19/003 ,  H03K19/0175

Abstract: An integrated circuit comprises a power input, digital logic circuitry, a plurality of charge stores, and obscuring circuitry. The charge stores are configured to receive power from the power input, are distributed through the digital logic circuitry and are capable of providing power to the digital logic circuitry. The obscuring circuitry is configured to obscure electromagnetic emissions associated with flow of current in current loops between the plurality of charge stores and the digital logic circuitry by switching between a plurality of different charge store activation patterns, wherein each charge store activation pattern describes a different selection of one or more of the plurality of charge stores providing power to the digital logic circuitry at a given time.

公开(公告)号：US11550733B2

公开(公告)日：2023-01-10

申请号：US16918938

申请日：2020-07-01

Applicant: Arm Limited

Inventor： Richard Andrew Paterson ,  Rainer Herberholz ,  Peter Andrew Rees Williams ,  Oded Golombek ,  Einat Luko

IPC: G06F12/14 ,  G06F21/53 ,  G06F21/56 ,  G06F21/75 ,  G06F21/76

Abstract: Disclosed are methods, systems and devices for storing states in a memory in support of applications residing in a trusted execution environment (TEE). In an implementation, one or more memory devices accessible by a memory controller may be shared between and/or among processes in an untrusted execution environment (UEE) and a TEE.

公开(公告)号：US10948963B2

公开(公告)日：2021-03-16

申请号：US16035884

申请日：2018-07-16

Applicant: ARM Limited

Inventor： Richard Andrew Paterson ,  Seow Chuan Lim ,  Alessandro Renzi

IPC: G06F1/28 ,  G06F1/3287 ,  G06F1/3209 ,  G06F11/30 ,  G06F1/3296

Abstract: An integrated circuit comprises first and second power domains, and a message handling unit to control passing of messages sent from a sender device in the first power domain to a receiver device in the second power domain. The message handling unit writes messages sent from the sender device to a message storage area, provided in the second power domain. The message handling unit is responsive to a message send request from the sender device requesting sending of at least one message to the receiver device when at least one device in the second power domain is in a quiescent state, to transmit a wakeup request to a second domain power controller to request that said at least one device in the second power domain transitions from the quiescent state to an awake state.

公开(公告)号：US10530562B2

公开(公告)日：2020-01-07

申请号：US15493429

申请日：2017-04-21

Applicant: ARM Limited

Inventor： Richard Andrew Paterson ,  Simon Crossley ,  Ramnath Bommu Subbiah Swamy ,  Steven Douglas Krueger ,  Anitha Kona

IPC: G06F1/12 ,  H04L12/26 ,  H04L7/00

Abstract: A method for correlating first and second local time counts in first and second integrated circuits is provided. The first and second integrated circuits communicate via a communication network. A separate time control signal path is also provided between the integrated circuits. The method comprises determining a signal propagation latency associated with propagation of a latency determining signal between the integrated circuits on the time control signal path, and correlating the first and second local time counts in dependence on the signal propagation latency and a time correlating signal transmitted on the time control signal path.

公开(公告)号：US11480613B2

公开(公告)日：2022-10-25

申请号：US17127846

申请日：2020-12-18

Applicant: Arm Limited

Inventor： Richard Andrew Paterson ,  Rainer Herberholz ,  Peter Andrew Rees Williams ,  Oded Golombek ,  Einat Luko ,  Jeffrey Scott Boyer

IPC: G01R31/3177 ,  G01R31/3187 ,  G01R31/317 ,  G01R31/3185 ,  G01R31/28 ,  H04L9/08

Abstract: Disclosed are methods, systems and devices for implementing built-in self-test (BIST) to be performed by an untrusted party and/or in an unsecure testing environment. In an embodiment, a test access port (TAP) on a device may enable a party to initiate execution of one or more BIST procedures on the device. Additionally, such a TAP may enable loading of encrypted instructions to be executed by one or more processors formed on a device under test.

公开(公告)号：US20220004622A1

公开(公告)日：2022-01-06

申请号：US16918938

申请日：2020-07-01

Applicant: Arm Limited

Inventor： Richard Andrew Paterson ,  Rainer Herberholz ,  Peter Andrew Rees Williams ,  Oded Golombek ,  Einat Luko

IPC: G06F21/53 ,  G06F21/76 ,  G06F21/75 ,  G06F21/56

Abstract: Disclosed are methods, systems and devices for storing states in a memory in support of applications residing in a trusted execution environment (TEE). In an implementation, one or more memory devices accessible by a memory controller may be shared between and/or among processes in an untrusted execution environment (UEE) and a TEE.

公开(公告)号：US10775862B2

公开(公告)日：2020-09-15

申请号：US16638839

申请日：2018-07-10

Applicant: ARM LIMITED

Inventor： Richard Andrew Paterson ,  Christopher Vincent Severino ,  Dominic William Brown ,  Seow Chuan Lim ,  Csaba Kelemen ,  Gergely Kiss

IPC: H03L7/00 ,  G06F1/24 ,  H03K19/00 ,  G06F1/3287

Abstract: An integrated circuit (2) has first and second domains (4). The first domain has a power controller (22) to control the power state of at least one device (20) in the second domain based on power management signals exchanged on a power management channel (24) between the first and second domains A reset isolation bridge (40) is provided on the power management channel (24) between the first and second domains (4). The bridge (40) has first and second interfaces (42, 44) to exchange the power management signals with the first and second domains respectively. Isolating circuitry (46) is provided in the bridge (40) to respond to a reset indication (8) indicating reset of one of the first and second domains, to isolate state transitions of the power management signals at the first and second interfaces (42, 44) from each other.