公开(公告)号：US07373484B1

公开(公告)日：2008-05-13

申请号：US10755692

申请日：2004-01-12

申请人： Arun Radhakrishnan ,  Benjamin T. Sander ,  Michael A. Filippo ,  Michael T. Clark ,  David E. Kroesche

发明人： Arun Radhakrishnan ,  Benjamin T. Sander ,  Michael A. Filippo ,  Michael T. Clark ,  David E. Kroesche

IPC分类号： G06F9/30

CPC分类号： G06F9/3842 ,  G06F9/3013 ,  G06F9/384

摘要： A method of controlling write operations to a non-renamed register space includes receiving a write operation to a given register within the non-renamed register space. The method also includes determining whether a pending write operation to the given register exists. In response to determining that the pending write operation to the given register exists, the method includes blocking the write operation to the given register from being scheduled. However, in response to determining that the pending write operation to the given register does not exist, the method includes allowing the write operation to the given register to be scheduled. Further, if the pending write operation to the given register does not exist, the method includes allowing a subsequent write operation to a different register within the non-renamed register space to be scheduled.

摘要翻译： 控制对未重新命名的寄存器空间的写入操作的方法包括：接收对非重命名寄存器空间内的给定寄存器的写操作。 该方法还包括确定是否存在对给定寄存器的挂起写入操作。 响应于确定对给定寄存器的挂起写入操作存在，该方法包括阻止对给定寄存器的写入操作被调度。 然而，响应于确定对给定寄存器的挂起写操作不存在，该方法包括允许对给定寄存器的写操作进行调度。 此外，如果对给定寄存器的挂起写入操作不存在，则该方法包括允许对未重新命名的寄存器空间内的不同寄存器的后续写入操作进行调度。

公开(公告)号：US07315935B1

公开(公告)日：2008-01-01

申请号：US10679745

申请日：2003-10-06

申请人： Mitchell Alsup ,  Brian D. McMinn ,  Benjamin T. Sander ,  David E. Kroesche

发明人： Mitchell Alsup ,  Brian D. McMinn ,  Benjamin T. Sander ,  David E. Kroesche

IPC分类号： G06F9/30 ,  G06F9/40 ,  G06F15/00

CPC分类号： G06F9/3836 ,  G06F9/30141 ,  G06F9/3828 ,  G06F9/3889

摘要： A microprocessor is configured to provide port arbitration in a register file. The microprocessor includes a plurality of functional units configured to collectively operate on a maximum number of operands in a given execution cycle, and a register file providing a number of read ports that is insufficient to provide the maximum number of operands to the plurality of functional units in the given execution cycle. The microprocessor also includes an arbitration logic coupled to allocate the read ports of the register file for use by selected functional units during the given execution cycle.

摘要翻译： 微处理器被配置为在寄存器文件中提供端口仲裁。 微处理器包括多个功能单元，其被配置为在给定执行周期中对最大数目的操作数进行集中操作;以及寄存器文件，其提供不足以向多个功能单元提供最大数目的操作数的多个读取端口 在给定的执行周期。 微处理器还包括一个仲裁逻辑，它被耦合以分配该寄存器文件的读取端口，供所选功能单元在给定的执行周期中使用。

公开(公告)号：US06968444B1

公开(公告)日：2005-11-22

申请号：US10287301

申请日：2002-11-04

申请人： David E. Kroesche ,  Michael T. Clark

发明人： David E. Kroesche ,  Michael T. Clark

IPC分类号： G06F9/30 ,  G06F9/38

CPC分类号： G06F9/3836 ,  G06F9/3822 ,  G06F9/3855

摘要： A microprocessor employing a fixed position dispatch unit. The microprocessor includes a plurality of execution units each corresponding to an issue position and configured to execute a common subset of instructions. At least a first one of the execution units includes extended logic for executing a designated instruction that others of the execution units may be incapable of executing. The microprocessor also includes a plurality of decoders coupled to the plurality of execution units. The plurality of decoders may provide positional information to cause the designated instruction to be routed to the first execution unit. Further, the microprocessor includes a dispatch control unit configured to dispatch during a dispatch cycle, the designated instruction for execution by the first execution unit based upon the positional information. The dispatch control unit may further dispatch one or more instructions within the common subset of instructions during the same dispatch cycle.

摘要翻译： 采用固定位置调度单元的微处理器。 微处理器包括多个执行单元，每个执行单元对应于发布位置并被配置为执行公共的指令子集。 执行单元中的至少第一个包括用于执行指定指令的扩展逻辑，其他执行单元可能不能执行。 微处理器还包括耦合到多个执行单元的多个解码器。 多个解码器可以提供位置信息以使指定的指令被路由到第一执行单元。 此外，微处理器包括调度控制单元，其被配置为在调度周期期间发送指定的指令，以由第一执行单元基于位置信息执行。 调度控制单元还可以在相同调度周期内在指令的公共子集内调度一个或多个指令。

公开(公告)号：US07730346B2

公开(公告)日：2010-06-01

申请号：US11742029

申请日：2007-04-30

申请人： David E. Kroesche ,  Swamy Punyamurtula

发明人： David E. Kroesche ,  Swamy Punyamurtula

IPC分类号： G06F11/00

CPC分类号： G06F11/1048 ,  G11C29/44 ,  G11C29/76 ,  G11C2029/0411 ,  G11C2029/1208

摘要： A method includes storing a first data to a first portion of a storage location of a storage component of a processing device in association with a first store operation and obtaining a second data from the storage location, the second data being stored at the storage location prior to the first data. The method further includes determining whether the storage location has a bit error at second portion of the storage location different from the first portion based on the second data obtained from the storage location. The method additionally includes storing a third data to a second portion of the storage location in response to determining the storage location has a bit error at the second portion, wherein the third data is to correct the bit error.

摘要翻译： 一种方法包括将第一数据存储到与第一存储操作相关联的处理设备的存储部件的存储位置的第一部分，并从存储位置获取第二数据，第二数据存储在存储位置之前 到第一个数据。 该方法还包括基于从存储位置获得的第二数据来确定存储位置是否存在与第一部分不同的存储位置的第二部分处的位错误。 该方法还包括响应于确定存储位置在第二部分处具有位错误而将第三数据存储到存储位置的第二部分，其中第三数据用于校正位错误。

公开(公告)号：US20080270824A1

公开(公告)日：2008-10-30

申请号：US11742029

申请日：2007-04-30

申请人： David E. Kroesche ,  Swamy Punyamurtula

发明人： David E. Kroesche ,  Swamy Punyamurtula

IPC分类号： G06F11/16

CPC分类号： G06F11/1048 ,  G11C29/44 ,  G11C29/76 ,  G11C2029/0411 ,  G11C2029/1208

摘要： A method includes storing a first data to a first portion of a storage location of a storage component of a processing device in association with a first store operation and obtaining a second data from the storage location, the second data being stored at the storage location prior to the first data. The method further includes determining whether the storage location has a bit error at second portion of the storage location different from the first portion based on the second data obtained from the storage location. The method additionally includes storing a third data to a second portion of the storage location in response to determining the storage location has a bit error at the second portion, wherein the third data is to correct the bit error.

摘要翻译： 一种方法包括将第一数据存储到与第一存储操作相关联的处理设备的存储部件的存储位置的第一部分，并从存储位置获取第二数据，第二数据存储在存储位置之前 到第一个数据。 该方法还包括基于从存储位置获得的第二数据来确定存储位置是否存在与第一部分不同的存储位置的第二部分处的位错误。 该方法还包括响应于确定存储位置在第二部分处具有位错误而将第三数据存储到存储位置的第二部分，其中第三数据用于校正位错误。

公开(公告)号：US20080244244A1

公开(公告)日：2008-10-02

申请号：US11694870

申请日：2007-03-30

申请人： Michael E. Tuuk ,  David E. Kroesche

发明人： Michael E. Tuuk ,  David E. Kroesche

IPC分类号： G06F9/30

CPC分类号： G06F11/1064

摘要： A method includes accessing, at a processing device, operand data associated with an instruction operation from a data cache and executing, at the processing device, the instruction operation using the operand data prior to determining the validity of the operand data. The method further includes retiring, at the processing device, the instruction operation in response to determining the operand data is valid. A processing device includes a data cache and an instruction pipeline. The instruction pipeline includes an execution stage configured to execute an instruction operation using operand data access from the data cache prior to determining the validity of the operand data and a retire stage configured to retire the instruction operation in response to determining the operand data is valid.

摘要翻译： 一种方法包括在处理设备处访问与数据高速缓存相关联的指令操作的操作数数据，并且在确定操作数数据的有效性之前，在处理设备处执行使用操作数数据的指令操作。 该方法还包括在处理装置处退出响应于确定操作数数据有效的指令操作。 处理装置包括数据高速缓存和指令流水线。 指令流水线包括执行阶段，其被配置为在确定操作数数据的有效性之前，使用来自数据高速缓存的操作数数据访问执行指令操作，以及响应于确定操作数数据有效而被配置为退出指令操作的退休阶段。

公开(公告)号：US5954816A

公开(公告)日：1999-09-21

申请号：US972988

申请日：1997-11-19

申请人： Thang M. Tran ,  David E. Kroesche ,  Karthikeyan Muthusamy ,  Andrew McBride

发明人： Thang M. Tran ,  David E. Kroesche ,  Karthikeyan Muthusamy ,  Andrew McBride

IPC分类号： G06F9/38

CPC分类号： G06F9/3844 ,  G06F9/30054 ,  G06F9/3806

摘要： A branch prediction unit includes a branch prediction entry corresponding to a group of contiguous instruction bytes. The branch prediction entry stores branch predictions corresponding to branch instructions within the group of contiguous instruction bytes. Additionally, the branch prediction entry stores a set of branch selectors corresponding to the group of contiguous instruction bytes. The branch selectors identify which branch prediction is to be selected if the corresponding byte (or bytes) is selected by the offset portion of the fetch address. Still further, a predicted branch selector is stored. The predicted branch selector is used to select a branch prediction for forming the fetch address. In parallel, a selected branch selector is selected from the set of branch selectors. The predicted branch selector is verified using the selected branch selector. If the selected branch selector and the predicted branch selector mismatch, the correct branch prediction is generated and the predicted branch selector is updated to indicate the selected branch selector.

摘要翻译： 分支预测单元包括对应于一组相邻指令字节的分支预测条目。 分支预测条目存储对应于连续指令字节组内的分支指令的分支预测。 此外，分支预测条目存储对应于该组连续指令字节的一组分支选择器。 如果通过提取地址的偏移部分选择了相应的字节（或字节），则分支选择器识别要选择哪个分支预测。 此外，存储预测分支选择器。 预测分支选择器用于选择用于形成取出地址的分支预测。 并行地，从分支选择器组中选择选择的分支选择器。 使用所选择的分支选择器验证预测分支选择器。 如果所选择的分支选择器和预测分支选择器不匹配，则生成正确的分支预测，并且更新预测分支选择器以指示所选择的分支选择器。