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    Multi-level routing architecture in a field programmable gate array having transmitters and receivers
    1.
    发明授权
    Multi-level routing architecture in a field programmable gate array having transmitters and receivers 失效
    具有发射机和接收机的现场可编程门阵列中的多级路由架构

    公开(公告)号：US07126374B2

    公开(公告)日：2006-10-24

    申请号：US11074922

    申请日：2005-03-07

    申请人： Arunangshu Kundu ,  Venkatesh Narayanan ,  John McCollum ,  William C. Plants

    发明人： Arunangshu Kundu ,  Venkatesh Narayanan ,  John McCollum ,  William C. Plants

    IPC分类号： H03K19/177

    CPC分类号： H03K19/17736

    摘要： A routing architecture in a field programmable gate array (FPGA) having a plurality of logic clusters wherein each logic cluster has at least two sub-clusters. The logic clusters are arranged in rows and columns and each logic clusters has a plurality of receiver components, a plurality of transmitter components, at least one buffer module, at least one sequential logic component and at least one combinatorial logic component. A first-level routing architecture is programmably coupled to the logic clusters and a second-level routing architecture is programmably coupled to the logic clusters and to the first-level routing architecture through at least one of the transmitter components and at least one of the receiver components.

    摘要翻译： 具有多个逻辑集群的现场可编程门阵列（FPGA）中的路由架构，其中每个逻辑集群具有至少两个子集群。 逻辑簇以行和列排列，并且每个逻辑簇具有多个接收器组件，多个发射器组件，至少一个缓冲器模块，至少一个顺序逻辑组件和至少一个组合逻辑组件。 第一级路由架构可编程地耦合到逻辑集群，并且第二级路由架构可编程地耦合到逻辑集群，并通过至少一个发送器部件和至少一个接收器耦合到第一级路由架构 组件。

    Multi-level routing architecture in a field programmable gate array having transmitters and receivers
    2.
    发明授权
    Multi-level routing architecture in a field programmable gate array having transmitters and receivers 有权
    具有发射机和接收机的现场可编程门阵列中的多级路由架构

    公开(公告)号：US07432733B1

    公开(公告)日：2008-10-07

    申请号：US11531375

    申请日：2006-09-13

    申请人： Arunangshu Kundu ,  Venkatesh Narayanan ,  John McCollum ,  William C. Plants

    发明人： Arunangshu Kundu ,  Venkatesh Narayanan ,  John McCollum ,  William C. Plants

    IPC分类号： H03K19/177

    CPC分类号： H03K19/17736

    摘要： A routing architecture in a field programmable gate array (FPGA) having a plurality of logic clusters wherein each logic cluster has at least two sub-clusters. The logic clusters are arranged in rows and columns and each logic clusters has a plurality of receiver components, a plurality of transmitter components, at least one buffer module, at least one sequential logic component and at least one combinatorial logic component. A first-level routing architecture is programmably coupled to the logic clusters and a second-level routing architecture is programmably coupled to the logic clusters and to the first-level routing architecture through at least one of the transmitter components and at least one of the receiver components.

    摘要翻译： 具有多个逻辑集群的现场可编程门阵列（FPGA）中的路由架构，其中每个逻辑集群具有至少两个子集群。 逻辑簇以行和列排列，并且每个逻辑簇具有多个接收器组件，多个发射器组件，至少一个缓冲器模块，至少一个顺序逻辑组件和至少一个组合逻辑组件。 第一级路由架构可编程地耦合到逻辑集群，并且第二级路由架构可编程地耦合到逻辑集群，并通过至少一个发送器部件和至少一个接收器耦合到第一级路由架构 组件。

    Field programmable gate array and microcontroller system-on-a-chip
    10.
    发明授权
    Field programmable gate array and microcontroller system-on-a-chip 有权
    现场可编程门阵列和微控制器片上系统

    公开(公告)号：US07516303B2

    公开(公告)日：2009-04-07

    申请号：US11187068

    申请日：2005-07-22

    申请人： Arunangshu Kundu ,  Arnold Goldfein ,  William C. Plants ,  David Hightower

    发明人： Arunangshu Kundu ,  Arnold Goldfein ,  William C. Plants ,  David Hightower

    IPC分类号： G06F15/00 ,  G06F15/76

    CPC分类号： G06F15/7842 ,  G06F15/7867

    摘要： A system-on-a-chip integrated circuit has a field programmable gate array core having logic clusters, static random access memory modules, and routing resources, a field programmable gate array virtual component interface translator having inputs and outputs, wherein the inputs are connected to the field programmable gate array core, a microcontroller, a microcontroller virtual component interface translator having input and outputs, wherein the inputs are connected to the microcontroller, a system bus connected to the outputs of the field programmable gate array virtual component interface translator and also to the outputs of said microcontroller virtual component interface translator, and direct connections between the microcontroller and the routing resources of the field programmable gate array core.

    摘要翻译： 片上系统集成电路具有具有逻辑集群，静态随机存取存储器模块和路由资源的现场可编程门阵列核心，具有输入和输出的现场可编程门阵列虚拟组件接口转换器，其中输入被连接 到现场可编程门阵列核心，微控制器，具有输入和输出的微控制器虚拟组件接口转换器，其中输入连接到微控制器，连接到现场可编程门阵列虚拟组件接口转换器的输出的系统总线，以及 到所述微控制器虚拟组件接口转换器的输出，以及微控制器与现场可编程门阵列核心的路由资源之间的直接连接。