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公开(公告)号：US07043596B2
公开(公告)日：2006-05-09
申请号：US10113060
申请日：2002-03-29
申请人： Thomas M. McWilliams , Jeffrey B. Rubin , Michael W. Parkin , Oyekunle A. Olukotun , Derek E. Pappas , Jeffrey M. Broughton , David R. Emberson , David S. Allison , Ashley N. Saulsbury , Earl T. Cohen , Nyles I. Nettleton , James B. Burr , Liang T. Chen
发明人： Thomas M. McWilliams , Jeffrey B. Rubin , Michael W. Parkin , Oyekunle A. Olukotun , Derek E. Pappas , Jeffrey M. Broughton , David R. Emberson , David S. Allison , Ashley N. Saulsbury , Earl T. Cohen , Nyles I. Nettleton , James B. Burr , Liang T. Chen
CPC分类号： G06F17/5022 , G06F15/8023 , H04L49/10 , H04L49/101
摘要： A method and apparatus for computation is provided. A main cluster crossbar is connected to a plurality of statically scheduled routing processors. A first sub-cluster crossbar is associated with a first one of the plurality of statically scheduled routing processors where the first sub-cluster crossbar is connected to a first plurality of execution processors. A second sub-cluster crossbar is associated with a second one of the plurality of statically scheduled routing processors where the second sub-cluster crossbar is connected to a second plurality of execution processors.
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2.发明授权Method and apparatus for controlling a massively parallel processing environment 有权用于控制大规模并行处理环境的方法和装置公开(公告)号：US06957318B2
公开(公告)日：2005-10-18
申请号：US10112118
申请日：2002-03-28
CPC分类号： G06F17/5022
摘要： A method for controlling a processor array by a host computer involves creating a graph of a plurality of nodes using a data connection component, configuring a broadcast tree from a spanning tree of the graph, propagating a first command from the host computer to a member of the processor array using the broadcast tree, configuring a reply tree from a spanning tree of the graph, transmitting a response from the member of the processor array to the host computer using the reply tree, and configuring the data connection component to send at least one message selected from the first command and the response on at least one run mode communication path.
摘要翻译： 用于由主计算机控制处理器阵列的方法包括使用数据连接组件创建多个节点的图形，从图表的生成树配置广播树，将第一命令从主计算机传播到主机的成员 使用所述广播树的所述处理器阵列，从所述图的生成树配置回复树，使用所述答复树将所述处理器阵列的成员的响应发送到所述主计算机，以及配置所述数据连接组件以发送至少一个 从第一命令中选择的消息和至少一个运行模式通信路径上的响应。
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公开(公告)号：US08633547B2
公开(公告)日：2014-01-21
申请号：US12140197
申请日：2008-06-16
申请人： Robert Masleid , James B. Burr , Michael Pelham
发明人： Robert Masleid , James B. Burr , Michael Pelham
IPC分类号： H01L29/76
CPC分类号： H01L23/535 , H01L23/52 , H01L23/585 , H01L27/0218 , H01L27/092 , H01L2924/0002 , H01L2924/00
摘要： Structures for spanning gap in body-bias voltage routing structure. In an embodiment, a structure is comprised of at least one metal wire.
摘要翻译： 体偏电压布线结构跨越间隙的结构。 在一个实施例中，结构由至少一根金属线构成。
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公开(公告)号：US08298896B2
公开(公告)日：2012-10-30
申请号：US13214593
申请日：2011-08-22
申请人： James B. Burr , Archisman Bagchi , Jawad Nasrullah
发明人： James B. Burr , Archisman Bagchi , Jawad Nasrullah
IPC分类号： H01L21/336
CPC分类号： H01L21/26513 , H01L29/1033 , H01L29/1083 , H01L29/7833
摘要： Systems and methods for raised source/drain with super steep retrograde channel are described. In accordance with a first embodiment, a semiconductor device comprises a substrate comprising a surface and a gate oxide disposed above the surface comprising a gate oxide thickness. The semiconductor device further comprises a super steep retrograde channel region formed at a depth below the surface. The depth is about ten to thirty times the gate oxide thickness. Embodiments may provide a more desirable body biasing voltage to threshold voltage characteristic than is available under the conventional art.
摘要翻译： 描述了具有超陡逆行通道的升高源极/漏极的系统和方法。 根据第一实施例，半导体器件包括包括表面的衬底和设置在包括栅极氧化物厚度的表面之上的栅极氧化物。 半导体器件还包括形成在表面下方深度的超陡逆行通道区域。 深度约为栅极氧化物厚度的十至三十倍。 实施例可以提供比常规技术中可获得的阈值电压特性更理想的主体偏置电压。
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公开(公告)号：US07949864B1
公开(公告)日：2011-05-24
申请号：US11238446
申请日：2005-09-28
申请人： Vjekoslav Svilan , James B. Burr
发明人： Vjekoslav Svilan , James B. Burr
CPC分类号： G06F1/3203 , G06F1/324 , G06F1/3296 , Y02D10/126 , Y02D10/172
摘要： Systems and methods of balanced adaptive body bias control. In accordance with a first embodiment of the present invention, a method of balanced adaptive body bias control comprises determining a desirable dynamic condition for circuitry of an integrated circuit. A first dynamic indicator corresponding to the desirable dynamic condition is accessed. Second and third dynamic indicators of the integrated circuit are accessed. A first body biasing voltage is adjusted by an increment so as to change the first dynamic indicator in the direction of the desirable dynamic condition. A second body biasing voltage is adjusted based on a relationship between the second dynamic indicator and the third dynamic indicator.
摘要翻译： 平衡自适应体偏置控制的系统和方法。 根据本发明的第一实施例，平衡自适应体偏置控制的方法包括确定用于集成电路的电路的期望的动态条件。 访问对应于期望的动态条件的第一动态指示符。 访问集成电路的第二和第三动态指示器。 通过增量来调整第一体偏置电压，以便在期望的动态条件的方向上改变第一动态指示器。 基于第二动态指示器和第三动态指示器之间的关系来调整第二身体偏置电压。
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6.发明申请SYSTEMS AND METHODS FOR INTEGRATED CIRCUITS COMPRISING MULTIPLE BODY BIASING DOMAINS 有权包含多个体积偏移域的集成电路的系统和方法公开(公告)号：US20110086478A1
公开(公告)日：2011-04-14
申请号：US12968032
申请日：2010-12-14
IPC分类号： H01L21/8238
CPC分类号： H03K19/0027 , H03K2217/0018
摘要： Systems and methods for integrated circuits comprising multiple body biasing domains. In accordance with a first embodiment, a semiconductor structure comprises a substrate of first type material. A first closed structure comprising walls of second type material extends from a surface of the substrate to a first depth. A planar deep well of said second type material underlying and coupled to the closed structure extends from the first depth to a second depth. The closed structure and the planar deep well of said second type material form an electrically isolated region of the first type material. A second-type semiconductor device is disposed to receive a first body biasing voltage from the electrically isolated region of the first type material. A well of the second-type material within the electrically isolated region of the first type material is formed and a first-type semiconductor device is disposed to receive a second body biasing voltage from the well of second-type material.
摘要翻译： 包括多个主体偏置域的集成电路的系统和方法。 根据第一实施例，半导体结构包括第一类型材料的衬底。 包括第二类型材料的壁的第一封闭结构从衬底的表面延伸到第一深度。 所述第二类型材料的下面并耦合到所述封闭结构的平面深井从所述第一深度延伸到第二深度。 所述第二类型材料的封闭结构和平面深孔形成第一类型材料的电隔离区域。 第二类型半导体器件设置成从第一类型材料的电隔离区域接收第一主体偏置电压。 形成在第一类型材料的电隔离区域内的第二类型材料的阱，并且设置第一类型半导体器件以从第二类型材料的阱接收第二主体偏置电压。
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7.发明申请SYSTEMS AND METHODS FOR INTEGRATED CIRCUITS COMPRISING MULTIPLE BODY BIASING DOMAINS 有权包含多个体积偏移域的集成电路的系统和方法公开(公告)号：US20100321098A1
公开(公告)日：2010-12-23
申请号：US12873062
申请日：2010-08-31
IPC分类号： H03K3/01
CPC分类号： H01L21/823892 , H01L21/743 , H01L21/761 , H01L21/823878 , H01L29/78
摘要： Systems and methods for integrated circuits comprising multiple body biasing domains. In accordance with a first embodiment of the present invention, a semiconductor structure comprises a substrate of first type material. A first closed structure comprising walls of second type material extends from a surface of the substrate to a first depth. A planar deep well of said second type material underlying and coupled to the closed structure extends from the first depth to a second depth. The closed structure and the planar deep well of said second type material form an electrically isolated region of the first type material. A second-type semiconductor device is disposed to receive a first body biasing voltage from the electrically isolated region of the first type material. A well of the second-type material within the electrically isolated region of the first type material is formed and a first-type semiconductor device is disposed to receive a second body biasing voltage from the well of second-type material.
摘要翻译： 包括多个主体偏置域的集成电路的系统和方法。 根据本发明的第一实施例，半导体结构包括第一类型材料的衬底。 包括第二类型材料的壁的第一封闭结构从衬底的表面延伸到第一深度。 所述第二类型材料的下面并耦合到所述封闭结构的平面深井从所述第一深度延伸到第二深度。 所述第二类型材料的封闭结构和平面深孔形成第一类型材料的电隔离区域。 第二类型半导体器件设置成从第一类型材料的电隔离区域接收第一主体偏置电压。 形成在第一类型材料的电隔离区域内的第二类型材料的阱，并且设置第一类型半导体器件以从第二类型材料的阱接收第二主体偏置电压。
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公开(公告)号：US07786756B1
公开(公告)日：2010-08-31
申请号：US11241552
申请日：2005-09-30
IPC分类号： H03K17/16 , H03K19/003 , H03K3/00
CPC分类号： G06F1/3203 , G06F1/305 , G06F1/324 , G06F1/3296 , Y02D10/126 , Y02D10/172
摘要： Systems and methods of suppressing latchup. In accordance with a first embodiment of the present invention a latchup suppression system comprises a voltage comparator for comparing a voltage applied to a body terminal of a semiconductor device to a reference voltage. The voltage comparator is also for controlling a selective coupling mechanism. The selective coupling mechanism is for selectively coupling the body terminal to a respective power supply. The latchup suppressing system is preferably independent of a voltage supply for applying a voltage to the body terminal.
摘要翻译： 抑制闭锁的系统和方法。 根据本发明的第一实施例，闭锁抑制系统包括用于将施加到半导体器件的主体端子的电压与参考电压进行比较的电压比较器。 电压比较器也用于控制选择性耦合机构。 选择性耦合机构用于将主体端子选择性地耦合到相应的电源。 闩锁抑制系统优选地独立于用于向身体终端施加电压的电压源。
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9.发明授权公开(公告)号：US07765412B1
公开(公告)日：2010-07-27
申请号：US11540117
申请日：2006-09-29
CPC分类号： G06F1/206 , G06F1/3203 , G06F1/324 , G06F1/3296 , Y02D10/126 , Y02D10/172
摘要： Methods and systems for operating a semiconductor device (e.g., a processor) are described. The device is operating at a first operating condition and device temperature. The first operating condition for the device can be dynamically changed to a second operating condition. The second operating condition is selected considering the design operating life of the device.
摘要翻译： 描述了用于操作半导体器件（例如，处理器）的方法和系统。 该设备在第一个操作条件和设备温度下运行。 设备的第一个操作条件可以动态地更改为第二个操作条件。 考虑到设备的设计使用寿命，选择第二个操作条件。
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公开(公告)号：US20100097092A1
公开(公告)日：2010-04-22
申请号：US12651244
申请日：2009-12-31
IPC分类号： G01R31/28
CPC分类号： H03K3/012 , G01R31/2621 , G05B13/021 , G06F1/3203 , G06F1/324 , G06F1/3296 , H03K3/0315 , Y02D10/126 , Y02D10/172
摘要： Systems and methods for closed loop feedback control of integrated circuits. In one embodiment, a plurality of controllable inputs to an integrated circuit is adjusted to achieve a predetermined value of a dynamic operating indicator of the integrated circuit. An operating condition of an integrated circuit is controlled via closed loop feedback based on dynamic operating indicators of the integrated circuit's behavior.
摘要翻译： 集成电路闭环反馈控制系统与方法。 在一个实施例中，调整集成电路的多个可控输入以实现集成电路的动态工作指示器的预定值。 基于集成电路行为的动态操作指示灯，通过闭环反馈来控制集成电路的工作状态。
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