利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

128 条记录 (耗时 0.036 秒)

    Resonator and filter using the same
    2.
    发明授权
    Resonator and filter using the same 失效
    谐振器和滤波器使用相同

    公开(公告)号：US07456707B2

    公开(公告)日：2008-11-25

    申请号：US11194460

    申请日：2005-08-02

    申请人： Naohiro Tsurumi ,  Kazuhiro Yahata ,  Yasuhiro Uemoto ,  Tsuyoshi Tanaka ,  Daisuke Ueda ,  Atsuhiko Kanda

    发明人： Naohiro Tsurumi ,  Kazuhiro Yahata ,  Yasuhiro Uemoto ,  Tsuyoshi Tanaka ,  Daisuke Ueda ,  Atsuhiko Kanda

    IPC分类号： H03H9/54

    CPC分类号： H03H9/173 ,  H03H3/04 ,  H03H9/172 ,  H03H9/564 ,  H03H2003/021

    摘要： An acoustic resonator includes: a substrate; a resonator film which is supported above the main surface of the substrate and includes a piezoelectric film and a pair of a top electrode and a bottom electrode which are formed on part of the top surface and part of the bottom surface of the piezoelectric film, respectively, to face each other via the piezoelectric film; and a support which is formed on the main surface of the substrate to support the resonator film from below. A resonance cavity is provided in part of a region between the substrate and the resonator film below at least a portion of part of the resonator film where the top electrode and the bottom electrode coincide with each other and an isolation cavity is provided in other part of said region where the support and the resonance cavity do not exist.

    摘要翻译： 声谐振器包括：基板; 一种谐振膜，其被支撑在基板的主表面上方，分别包括压电膜和一对顶电极和底电极，它们分别形成在压电膜的顶表面和底表面的一部分上 通过压电膜相互面对; 以及形成在基板的主表面上以从下方支撑谐振膜的支撑体。 谐振腔被设置在基板和谐振器膜之间的区域的一部分的下方，在谐振膜的至少一部分之上，其中顶部电极和底部电极彼此重合，并且在另一部分中设置隔离腔 所述区域不存在支撑和谐振腔。

    Resonator and filter using the same
    4.
    发明申请
    Resonator and filter using the same 失效
    谐振器和滤波器使用相同

    公开(公告)号：US20060038636A1

    公开(公告)日：2006-02-23

    申请号：US11194460

    申请日：2005-08-02

    申请人： Naohiro Tsurumi ,  Kazuhiro Yahata ,  Yasuhiro Uemoto ,  Tsuyoshi Tanaka ,  Daisuke Ueda ,  Atsuhiko Kanda

    发明人： Naohiro Tsurumi ,  Kazuhiro Yahata ,  Yasuhiro Uemoto ,  Tsuyoshi Tanaka ,  Daisuke Ueda ,  Atsuhiko Kanda

    IPC分类号： H03H9/58

    CPC分类号： H03H9/173 ,  H03H3/04 ,  H03H9/172 ,  H03H9/564 ,  H03H2003/021

    摘要： An acoustic resonator includes: a substrate; a resonator film which is supported above the main surface of the substrate and includes a piezoelectric film and a pair of a top electrode and a bottom electrode which are formed on part of the top surface and part of the bottom surface of the piezoelectric film, respectively, to face each other via the piezoelectric film; and a support which is formed on the main surface of the substrate to support the resonator film from below. A resonance cavity is provided in part of a region between the substrate and the resonator film below at least a portion of part of the resonator film where the top electrode and the bottom electrode coincide with each other and an isolation cavity is provided in other part of said region where the support and the resonance cavity do not exist.

    摘要翻译： 声谐振器包括：基板; 一种谐振膜，其被支撑在基板的主表面上方，分别包括压电膜和一对顶电极和底电极，它们分别形成在压电膜的顶表面和底表面的一部分上 通过压电膜相互面对; 以及形成在基板的主表面上以从下方支撑谐振膜的支撑体。 谐振腔被设置在基板和谐振器膜之间的区域的一部分的下方，在谐振膜的至少一部分之上，其中顶部电极和底部电极彼此重合，并且在另一部分中设置隔离腔 所述区域不存在支撑和谐振腔。

    Semiconductor device and method for fabricating the same
    5.
    发明授权
    Semiconductor device and method for fabricating the same 有权
    半导体装置及其制造方法

    公开(公告)号：US07247891B2

    公开(公告)日：2007-07-24

    申请号：US10970026

    申请日：2004-10-22

    申请人： Atsuhiko Kanda ,  Tsuyoshi Tanaka ,  Yasuhiro Uemoto ,  Yutaka Hirose ,  Tomohiro Murata

    发明人： Atsuhiko Kanda ,  Tsuyoshi Tanaka ,  Yasuhiro Uemoto ,  Yutaka Hirose ,  Tomohiro Murata

    IPC分类号： H01L29/739

    CPC分类号： H01L29/7787 ,  H01L27/14609 ,  H01L27/1463 ,  H01L27/14636 ,  H01L27/14656 ,  H01L29/2003 ,  H01L29/66462

    摘要： A semiconductor device has a first nitride semiconductor layer, a second nitride semiconductor layer formed on the first nitride semiconductor layer and having such a composition as to generate a 2-dimensional electron gas layer in the upper portion of the first nitride semiconductor layer, and an electrode having an ohmic property and formed selectively on the second nitride semiconductor layer. The second nitride semiconductor layer includes a contact area having at least one inclined portion with a bottom or wall surface thereof being inclined toward the upper surface of the first nitride semiconductor layer and defining a depressed cross-sectional configuration. The electrode is formed on the contact area.

    摘要翻译： 半导体器件具有第一氮化物半导体层，形成在第一氮化物半导体层上的第二氮化物半导体层，并具有在第一氮化物半导体层的上部产生二维电子气层的组成， 电极，其选择性地形成在第二氮化物半导体层上。 第二氮化物半导体层包括具有至少一个倾斜部分的接触区域，其底部或壁表面朝向第一氮化物半导体层的上表面倾斜并且限定凹陷的横截面构型。 电极形成在接触区域上。

    Semiconductor device
    8.
    发明授权
    Semiconductor device 有权
    半导体器件

    公开(公告)号：US07528423B2

    公开(公告)日：2009-05-05

    申请号：US11681408

    申请日：2007-03-02

    申请人： Hiroaki Ueno ,  Tetsuzo Ueda ,  Yasuhiro Uemoto ,  Daisuke Ueda ,  Tsuyoshi Tanaka ,  Manabu Yanagihara ,  Yutaka Hirose ,  Masahiro Hikita

    发明人： Hiroaki Ueno ,  Tetsuzo Ueda ,  Yasuhiro Uemoto ,  Daisuke Ueda ,  Tsuyoshi Tanaka ,  Manabu Yanagihara ,  Yutaka Hirose ,  Masahiro Hikita

    IPC分类号： H01L31/072 ,  H01L31/109

    CPC分类号： H01L29/7786 ,  H01L29/2003

    摘要： It is an object of the present invention to provide a semiconductor device, which can simultaneously achieve a normally-off mode of HFET and an improvement in Imax, and further achieve an improvement in gm and a reduction in gate leakage current. In order to keep a thin barrier layer 13 on an operation layer 12 of a substrate 11 directly under a gate electrode for mostly contributing to achieve the normally-off mode and also implement the high Imax, it is configured in such a way that a thickness of the barrier layer 13 can be increased by the semiconductor layer 17 between gate and source regions and between gate and drain regions. It is therefore possible to achieve the normally-off mode and an improvement in Imax as compared with an FET in which a thickness of the barrier layer is designed so as to be uniform. An insulating film 18 with a dielectric constant higher than that of the barrier layer is further inserted between a gate electrode 16 and the barrier layers 13, so that an improvement in gm and a reduction in gate leakage current can be achieved.

    摘要翻译： 本发明的一个目的是提供一种可以同时实现HFET的常闭模式和改进Imax的半导体器件，并进一步实现gm的改善和栅极漏电流的减小。 为了在栅电极正下方的基板11的操作层12上保持薄的阻挡层13，主要用于实现常关模式并且还实现了高的Imax，它被配置成使得厚度 可以通过栅极和源极区域之间以及栅极和漏极区域之间的半导体层17来增加阻挡层13。 因此，与设置阻挡层的厚度均匀的FET相比，可以实现常闭模式和Imax的改善。 介电常数高于阻挡层的绝缘膜18进一步插入在栅电极16和阻挡层13之间，从而可以实现gm的改善和栅极漏电流的减小。

    SEMICONDUCTOR DEVICE
    9.
    发明申请
    SEMICONDUCTOR DEVICE 有权
    半导体器件

    公开(公告)号：US20070210332A1

    公开(公告)日：2007-09-13

    申请号：US11681408

    申请日：2007-03-02

    申请人： Hiroaki UENO ,  Tetsuzo Ueda ,  Yasuhiro Uemoto ,  Daisuke Ueda ,  Tsuyoshi Tanaka ,  Manabu Yanagihara ,  Yutaka Hirose ,  Masahiro Hikita

    发明人： Hiroaki UENO ,  Tetsuzo Ueda ,  Yasuhiro Uemoto ,  Daisuke Ueda ,  Tsuyoshi Tanaka ,  Manabu Yanagihara ,  Yutaka Hirose ,  Masahiro Hikita

    IPC分类号： H01L31/00

    CPC分类号： H01L29/7786 ,  H01L29/2003

    摘要： It is an object of the present invention to provide a semiconductor device, which can simultaneously achieve a normally-off mode of HFET and an improvement in Imax, and further achieve an improvement in gm and a reduction in gate leakage current. In order to keep a thin barrier layer 13 on an operation layer 12 of a substrate 11 directly under a gate electrode for mostly contributing to achieve the normally-off mode and also implement the high Imax, it is configured in such a way that a thickness of the barrier layer 13 can be increased by the semiconductor layer 17 between gate and source regions and between gate and drain regions. It is therefore possible to achieve the normally-off mode and an improvement in Imax as compared with an FET in which a thickness of the barrier layer is designed so as to be uniform. An insulating film 18 with a dielectric constant higher than that of the barrier layer is further inserted between a gate electrode 16 and the barrier layers 13, so that an improvement in gm and a reduction in gate leakage current can be achieved.

    摘要翻译： 本发明的一个目的是提供一种半导体器件，其可以同时实现HFET的常闭模式和改进的最大值，并进一步实现gm的改善 和栅极漏电流的减小。 为了在栅电极正下方的基板11的操作层12上保持薄势垒层13，主要用于实现常关模式并且还实现高I max， 配置成使得栅极和源极区域之间以及栅极和漏极区域之间的半导体层17可以增加阻挡层13的厚度。 因此与阻挡层的厚度被设计为均匀的FET相比，可以实现常关模式和I 的改善。 介电常数高于阻挡层的绝缘膜18进一步插入在栅电极16和阻挡层13之间，从而改善gm和栅极漏电流的减小 可以实现。

    Semiconductor device
    10.
    发明申请
    Semiconductor device 有权
    半导体器件

    公开(公告)号：US20060157729A1

    公开(公告)日：2006-07-20

    申请号：US11325340

    申请日：2006-01-05

    申请人： Hiroaki Ueno ,  Tetsuzo Ueda ,  Yasuhiro Uemoto ,  Daisuke Ueda ,  Tsuyoshi Tanaka ,  Manabu Yanagihara ,  Yutaka Hirose ,  Masahiro Hikita

    发明人： Hiroaki Ueno ,  Tetsuzo Ueda ,  Yasuhiro Uemoto ,  Daisuke Ueda ,  Tsuyoshi Tanaka ,  Manabu Yanagihara ,  Yutaka Hirose ,  Masahiro Hikita

    IPC分类号： H01L33/00

    CPC分类号： H01L29/7786 ,  H01L29/2003

    摘要： It is an object of the present invention to provide a semiconductor device, which can simultaneously achieve a normally-off mode of HFET and an improvement in Imax, and further achieve an improvement in gm and a reduction in gate leakage current. In order to keep a thin barrier layer 13 on an operation layer 12 of a substrate 11 directly under a gate electrode for mostly contributing to achieve the normally-off mode and also implement the high Imax, it is configured in such a way that a thickness of the barrier layer 13 can be increased by the semiconductor layer 17 between gate and source regions and between gate and drain regions. It is therefore possible to achieve the normally-off mode and an improvement in Imax as compared with an FET in which a thickness of the barrier layer is designed so as to be uniform. An insulating film 18 with a dielectric constant higher than that of the barrier layer is further inserted between a gate electrode 16 and the barrier layers 13, so that an improvement in gm and a reduction in gate leakage current can be achieved.

    摘要翻译： 本发明的一个目的是提供一种半导体器件，其可以同时实现HFET的常闭模式和改进的最大值，并进一步实现gm的改善 和栅极漏电流的减小。 为了在栅电极正下方的基板11的操作层12上保持薄势垒层13，主要用于实现常关模式并且还实现高I max， 配置成使得栅极和源极区域之间以及栅极和漏极区域之间的半导体层17可以增加阻挡层13的厚度。 因此与阻挡层的厚度被设计为均匀的FET相比，可以实现常关模式和I 的改善。 介电常数高于阻挡层的绝缘膜18进一步插入在栅电极16和阻挡层13之间，从而改善gm和栅泄漏电流的降低 可以实现。