公开(公告)号：US06184553B2

公开(公告)日：2001-02-06

申请号：US09325772

申请日：1999-06-04

申请人： Shinji Odanaka ,  Kaori Akamatsu ,  Junichi Kato ,  Atsushi Hori ,  Seiki Ogura

发明人： Shinji Odanaka ,  Kaori Akamatsu ,  Junichi Kato ,  Atsushi Hori ,  Seiki Ogura

IPC分类号： H07L27115

CPC分类号： H01L29/66825 ,  H01L21/28273 ,  H01L29/42324 ,  H01L29/7885

摘要： In a semiconductor substrate having a surface including a first surface region at a first level, a second surface region at a second level lower than the first level, and a step side region linking the first surface region and the second surface region together, a channel region has a triple structure. Thus, a high electric field is formed in a corner portion between the step side region and the second surface region and in the vicinity thereof. A high electric field is also formed in the first surface region. As a result, the efficiency, with which electrons are injected into a floating gate, is considerably increased.

公开(公告)号：US06051860A

公开(公告)日：2000-04-18

申请号：US8572

申请日：1998-01-16

申请人： Shinji Odanaka ,  Kaori Akamatsu ,  Junichi Kato ,  Atsushi Hori ,  Seiki Ogura

发明人： Shinji Odanaka ,  Kaori Akamatsu ,  Junichi Kato ,  Atsushi Hori ,  Seiki Ogura

IPC分类号： H01L21/8247 ,  H01L21/28 ,  H01L21/336 ,  H01L27/115 ,  H01L29/423 ,  H01L29/788 ,  H01L29/792 ,  H01L29/72

CPC分类号： H01L29/66825 ,  H01L21/28273 ,  H01L29/42324 ,  H01L29/7885

摘要： In a semiconductor substrate having a surface including a first surface region at a first level, a second surface region at a second level lower than the first level, and a step side region linking the first surface region and the second surface region together, a channel region has a triple structure. Thus, a high electric field is formed in a corner portion between the step side region and the second surface region and in the vicinity thereof. A high electric field is also formed in the first surface region. As a result, the efficiency, with which electrons are injected into a floating gate, is considerably increased.

摘要翻译： 在具有包括第一水平的第一表面区域的表面的半导体衬底中，具有低于第一水平的第二水平的第二表面区域和将第一表面区域和第二表面区域连接在一起的阶梯侧区域，通道 区域有三重结构。 因此，在台阶侧区域和第二表面区域之间的角部及其附近形成高电场。 在第一表面区域也形成高电场。 结果，电子注入浮栅的效率大大增加。

公开(公告)号：US06380585B1

公开(公告)日：2002-04-30

申请号：US09588308

申请日：2000-06-06

申请人： Shinji Odanaka ,  Kaori Akamatsu ,  Junichi Kato ,  Atsushi Hori ,  Seiki Ogura

发明人： Shinji Odanaka ,  Kaori Akamatsu ,  Junichi Kato ,  Atsushi Hori ,  Seiki Ogura

IPC分类号： H01L29788

CPC分类号： H01L29/66825 ,  H01L29/42324 ,  H01L29/7885

摘要： The nonvolatile semiconductor memory device of the present invention includes: a semiconductor substrate having a surface including a first surface region at a first level, a second surface region at a second level lower than the first level, and a step side region linking the first surface region and the second surface region together; a channel region formed in the first surface region of the semiconductor substrate; a source region and a drain region which are formed in the surface of the semiconductor substrate so as to interpose the channel region therebetween; a first insulating film formed on the surface of the semiconductor substrate; a floating gate formed on the first insulating film; a second insulating film formed on the floating gate; and a control gate which is capacitively coupled to the floating gate via the second insulating film. The drain region includes a low-concentration impurity layer which is formed in the second surface region and which has one end extending toward the step side region, and a high-concentration impurity layer which is connected to the low-concentration impurity layer and which is formed in a region distant from the channel region. As impurity concentration of the low-concentration impurity layer is lower than an impurity concentration of the high-concentration impurity layer. The floating gate covers the step side region and at least a part of the low-concentration impurity layer via the first insulating film.

摘要翻译： 本发明的非易失性半导体存储器件包括：半导体衬底，具有包括第一层的第一表面区域，低于第一层次的第二层的第二表面区域和将第一表面 区域和第二表面区域在一起; 形成在所述半导体衬底的所述第一表面区域中的沟道区; 源极区域和漏极区域，其形成在半导体衬底的表面中，以便在其间插入沟道区域; 形成在所述半导体衬底的表面上的第一绝缘膜; 形成在第一绝缘膜上的浮栅; 形成在浮动栅极上的第二绝缘膜; 以及通过第二绝缘膜电容耦合到浮动栅极的控制栅极。 漏区包括形成在第二表面区域中并且具有朝向台阶侧区域延伸的一端的低浓度杂质层和连接到低浓度杂质层的高浓度杂质层， 形成在远离通道区域的区域中。 由于低浓度杂质层的杂质浓度低于高浓度杂质层的杂质浓度。 浮置栅极经由第一绝缘膜覆盖台阶侧区域和至少一部分低浓度杂质层。

公开(公告)号：US06358799B2

公开(公告)日：2002-03-19

申请号：US09727536

申请日：2000-12-04

申请人： Shinji Odanaka ,  Kaori Akamatsu ,  Junichi Kato ,  Atsushi Hori ,  Seiki Ogura

发明人： Shinji Odanaka ,  Kaori Akamatsu ,  Junichi Kato ,  Atsushi Hori ,  Seiki Ogura

IPC分类号： H01L21336

CPC分类号： H01L29/66825 ,  H01L21/28273 ,  H01L29/42324 ,  H01L29/7885

摘要： In a semiconductor substrate having a surface including a first surface region at a first level, a second surface region at a second level lower than the first level, and a step side region linking the first surface region and the second surface region together, a channel region has a triple structure. Thus, a high electric field is formed in a corner portion between the step side region and the second surface region and in the vicinity thereof. A high electric field is also formed in the first surface region. As a result, the efficiency, with which electrons are injected into a floating gate, is considerably increased.

摘要翻译： 在具有包括第一水平的第一表面区域的表面的半导体衬底中，具有低于第一水平的第二水平的第二表面区域和将第一表面区域和第二表面区域连接在一起的阶梯侧区域，通道 区域有三重结构。 因此，在台阶侧区域和第二表面区域之间的角部及其附近形成高电场。 在第一表面区域也形成高电场。 结果，电子注入浮栅的效率大大增加。

公开(公告)号：US6121655A

公开(公告)日：2000-09-19

申请号：US848

申请日：1997-12-30

申请人： Shinji Odanaka ,  Kaori Akamatsu ,  Junichi Kato ,  Atsushi Hori ,  Seiki Ogura

发明人： Shinji Odanaka ,  Kaori Akamatsu ,  Junichi Kato ,  Atsushi Hori ,  Seiki Ogura

IPC分类号： G11C16/04 ,  H01L21/336 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/423 ,  H01L29/788 ,  H01L29/792 ,  H01L29/76

CPC分类号： H01L29/66825 ,  H01L29/42324 ,  H01L29/7885

摘要： The nonvolatile semiconductor memory device of the present invention includes: a semiconductor substrate having a surface including a first surface region at a first level, a second surface region at a second level lower than the first level, and a step side region linking the first surface region and the second surface region together; a channel region formed in the first surface region of the semiconductor substrate; a source region and a drain region which are formed in the surface of the semiconductor substrate so as to interpose the channel region therebetween; a first insulating film formed on the surface of the semiconductor substrate; a floating gate formed on the first insulating film; a second insulating film formed on the floating gate; and a control gate which is capacitively coupled to the floating gate via the second insulating film. The drain region includes a low-concentration impurity layer which is formed in the second surface region and which has one end extending toward the step side region, and a high-concentration impurity layer which is connected to the low-concentration impurity layer and which is formed in a region distant from the channel region. As impurity concentration of the low-concentration impurity layer is lower than an impurity concentration of the high-concentration impurity layer. The floating gate covers the step side region and at least a part of the low-concentration impurity layer via the first insulating film.

摘要翻译： 本发明的非易失性半导体存储器件包括：半导体衬底，具有包括第一层的第一表面区域，低于第一层次的第二层的第二表面区域和将第一表面 区域和第二表面区域在一起; 形成在所述半导体衬底的所述第一表面区域中的沟道区; 源极区域和漏极区域，其形成在半导体衬底的表面中，以便在其间插入沟道区域; 形成在所述半导体衬底的表面上的第一绝缘膜; 形成在第一绝缘膜上的浮栅; 形成在浮动栅极上的第二绝缘膜; 以及通过第二绝缘膜电容耦合到浮动栅极的控制栅极。 漏区包括形成在第二表面区域中并且具有朝向台阶侧区域延伸的一端的低浓度杂质层和连接到低浓度杂质层的高浓度杂质层， 形成在远离通道区域的区域中。 由于低浓度杂质层的杂质浓度低于高浓度杂质层的杂质浓度。 浮置栅极经由第一绝缘膜覆盖台阶侧区域和至少一部分低浓度杂质层。

公开(公告)号：US6147379A

公开(公告)日：2000-11-14

申请号：US58803

申请日：1998-04-13

申请人： Atsushi Hori ,  Junichi Kato ,  Shinji Odanaka ,  Seiki Ogura ,  Kaori Akamatsu

发明人： Atsushi Hori ,  Junichi Kato ,  Shinji Odanaka ,  Seiki Ogura ,  Kaori Akamatsu

IPC分类号： H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

CPC分类号： H01L29/7885

摘要： The nonvolatile semiconductor memory device of the invention includes: a semiconductor substrate having a surface including a first surface region at a first level, a second surface region at a second level lower than the first level, and a step side region linking the first and second surface regions; a channel region formed in the first surface region of the semiconductor substrate; a source region and a drain region which are formed in the surface of the semiconductor substrate so as to interpose the channel region therebetween; a first insulating film formed on the surface of the semiconductor substrate; a floating gate formed on the first insulating film; and a control gate capacitively coupled to the floating gate via a second insulating film. The first surface region is an upper surface of an epitaxially grown layer formed on the second surface region. The drain region includes: a low-concentration impurity layer formed in the second surface region and having one end extending toward the step side region; and a high-concentration impurity layer connected to the low-concentration impurity layer and formed in a region distant from the channel region. An impurity concentration of the low-concentration impurity layer is lower than that of the high-concentration impurity layer. The floating gate covers the step side region and at least a part of the low-concentration impurity layer via the first insulating film.

摘要翻译： 本发明的非易失性半导体存储器件包括：半导体衬底，具有包括第一电平的第一表面区域，低于第一电平的第二电平的第二表面区域和连接第一和第二电极的台阶侧区域的表面 表面区域 形成在所述半导体衬底的所述第一表面区域中的沟道区; 源极区域和漏极区域，其形成在半导体衬底的表面中，以便在其间插入沟道区域; 形成在所述半导体衬底的表面上的第一绝缘膜; 形成在第一绝缘膜上的浮栅; 以及经由第二绝缘膜电容耦合到浮置栅极的控制栅极。 第一表面区域是形成在第二表面区域上的外延生长层的上表面。 漏极区域包括：形成在第二表面区域中并且具有朝向台阶侧区域延伸的一端的低浓度杂质层; 以及连接到低浓度杂质层并形成在远离沟道区的区域中的高浓度杂质层。 低浓度杂质层的杂质浓度低于高浓度杂质层的杂质浓度。 浮置栅极经由第一绝缘膜覆盖台阶侧区域和至少一部分低浓度杂质层。

公开(公告)号：US06303438B1

公开(公告)日：2001-10-16

申请号：US09017216

申请日：1998-02-02

申请人： Atsushi Hori ,  Junichi Kato ,  Shinji Odanaka ,  Seiki Ogura

发明人： Atsushi Hori ,  Junichi Kato ,  Shinji Odanaka ,  Seiki Ogura

IPC分类号： H01L21336

CPC分类号： H01L29/66825 ,  H01L21/28273 ,  H01L29/42336 ,  H01L29/7885

摘要： The nonvolatile semiconductor memory device of the present invention includes: a semiconductor substrate having a surface including a first surface region at a first level, a second surface region at a second level lower than the first level, and a step side region linking the first surface region and the second surface region together; a channel region formed in the first surface region of the semiconductor substrate; a source region and a drain region which are formed in the surface of the semiconductor substrate so as to interpose the channel region therebetween; a first insulating film formed on the surface of the semiconductor substrate; a floating gate formed on the first insulating film; and a control gate which is capacitively coupled to the floating gate via a second insulating film. The first insulating film includes a first gate insulating film portion formed in the first surface region, and, a second gate insulating film portion formed in the step side region and the second surface region. The control gate is formed on the first gate insulating film portion. A part of the floating gate faces the step side region via the second gate insulating film portion, and another part of the floating gate is adjacent to the control gate via the second insulating film.

摘要翻译： 本发明的非易失性半导体存储器件包括：半导体衬底，具有包括第一层的第一表面区域，低于第一层次的第二层的第二表面区域和将第一表面 区域和第二表面区域在一起; 形成在所述半导体衬底的所述第一表面区域中的沟道区; 源极区域和漏极区域，其形成在半导体衬底的表面中，以便在其间插入沟道区域; 形成在所述半导体衬底的表面上的第一绝缘膜; 形成在第一绝缘膜上的浮栅; 以及通过第二绝缘膜电容耦合到浮置栅极的控制栅极。 第一绝缘膜包括形成在第一表面区域中的第一栅极绝缘膜部分和形成在台阶侧区域和第二表面区域中的第二栅极绝缘膜部分。 控制栅极形成在第一栅极绝缘膜部分上。 浮栅的一部分经由第二栅极绝缘膜部分面对台阶侧区域，浮栅的另一部分经由第二绝缘膜与控制栅极相邻。

公开(公告)号：US5675168A

公开(公告)日：1997-10-07

申请号：US415928

申请日：1995-04-03

申请人： Kyoji Yamashita ,  Shinji Odanaka ,  Kazumi Kurimoto ,  Akira Hiroki ,  Isao Miyanaga ,  Atsushi Hori

发明人： Kyoji Yamashita ,  Shinji Odanaka ,  Kazumi Kurimoto ,  Akira Hiroki ,  Isao Miyanaga ,  Atsushi Hori

IPC分类号： H01L27/02 ,  H01L27/088 ,  H01L29/08 ,  H01L29/78 ,  H01L23/60

CPC分类号： H01L27/0266 ,  H01L27/088 ,  H01L29/0847 ,  H01L29/7835 ,  H01L2924/0002

摘要： An unsymmetrical MOS device is disclosed which includes a semiconductor layer of a first conductive type having a surface having a first area and a second area which is offset from the first area; a gate insulator layer located on the first area of the surface of the semiconductor layer; a gate electrode located on the gate insulator layer; and a source region of a second conductive type and a drain region of the second conductive type each located in the semiconductor layer below the second area of the surface. The electric resistance of an area between the first area of the surface and the surface of the source region is smaller than the electric resistance of an area between the first area of the surface and the surface of the drain region.

摘要翻译： 公开了一种不对称MOS器件，其包括具有第一区域的表面的第一导电类型的半导体层和与第一区域偏移的第二区域; 位于所述半导体层表面的第一区域上的栅极绝缘体层; 位于栅极绝缘体层上的栅电极; 以及第二导电类型的源极区域和第二导电类型的漏极区域，每个位于该表面的第二区域下方的半导体层中。 表面的第一区域和源区域的表面之间的区域的电阻小于表面的第一区域和漏极区域的表面之间的区域的电阻。

公开(公告)号：US5514893A

公开(公告)日：1996-05-07

申请号：US207426

申请日：1994-03-08

申请人： Isao Miyanaga ,  Kazumi Kurimoto ,  Atsushi Hori ,  Shinji Odanaka

发明人： Isao Miyanaga ,  Kazumi Kurimoto ,  Atsushi Hori ,  Shinji Odanaka

IPC分类号： H01L27/02 ,  H03K19/003 ,  H01L23/62 ,  H02H3/20 ,  H02H9/00 ,  H03K17/60

CPC分类号： H01L27/0259 ,  H01L27/0266 ,  H03K19/00315

摘要： A semiconductor device includes an input/output terminal, an internal circuit connected to the input/output terminal, a first terminal for providing a first electrical potential, and a second terminal for providing a second electrical potential which is lower than the first electrical potential, the device further including: a first n-channel MOS transistor having a drain connected to the input/output terminal, a source connected to the second terminal, and a gate to be electrically connected to the first terminal; and a first switching element for switching between an electrically conductive state and a non-conductive state between the drain and the gate of the first n-channel MOS transistor, the switching element forming the electrically conductive state between the drain and the gate of the first n-channel MOS transistor when 1) a surge voltage lower than the first electrical potential is applied to the input/output terminal, and 2) an electrical potential difference between the drain and the gate of the first n-channel MOS transistor exceeds a predetermined voltage lower than a breakdown voltage of the gate of the first n-channel MOS transistor. The formation of the electrically conductive state prevents the gate oxide of the first n-channel MOS transistor from being damaged.

摘要翻译： 半导体器件包括输入/​​输出端子，连接到输入/输出端子的内部电路，用于提供第一电位的第一端子和用于提供低于第一电位的第二电位的第二端子， 该器件还包括：第一n沟道MOS晶体管，具有连接到输入/输出端子的漏极，连接到第二端子的源极和与第一端子电连接的栅极; 以及用于在第一n沟道MOS晶体管的漏极和栅极之间切换导电状态和非导通状态的第一开关元件，所述开关元件在第一N沟道MOS晶体管的漏极和栅极之间形成导电状态 n沟道MOS晶体管，当1）低于第一电位的浪涌电压被施加到输入/输出端时，以及2）第一n沟道MOS晶体管的漏极和栅极之间的电位差超过预定的 电压低于第一n沟道MOS晶体管的栅极的击穿电压。 导电状态的形成防止了第一n沟道MOS晶体管的栅极氧化物被损坏。

公开(公告)号：US6051465A

公开(公告)日：2000-04-18

申请号：US126272

申请日：1998-07-30

申请人： Junichi Kato ,  Atsushi Hori

发明人： Junichi Kato ,  Atsushi Hori

IPC分类号： H01L21/336 ,  H01L21/8247

CPC分类号： H01L29/66825

摘要： A method for fabricating a nonvolatile semiconductor memory device according to the present invention includes the steps of: forming a first mask to define a channel of a memory cell in a semiconductor substrate; doping an impurity into the semiconductor substrate by using the first mask, thereby forming a first doped region in the semiconductor substrate; forming a second mask so as to overlap at least one of a first region of the semiconductor substrate where a source is to be formed and a second region of the semiconductor substrate where a drain is to be formed and at least part of the first mask; etching the semiconductor substrate by using the first and second masks, thereby forming a recessed portion in a region of the semiconductor substrate that is not covered with the first and second masks; forming a second doped region in the recessed portion of the semiconductor substrate; and removing the first and second masks, and forming a gate structure including a first insulating film, a floating gate electrode, a second insulating film and a control gate electrode at least over a side surface of the recessed portion and the channel defined by the first mask.

摘要翻译： 根据本发明的制造非易失性半导体存储器件的方法包括以下步骤：形成第一掩模以限定半导体衬底中的存储单元的沟道; 通过使用第一掩模将杂质掺杂到半导体衬底中，从而在半导体衬底中形成第一掺杂区; 形成第二掩模，以便与要形成源极的半导体衬底的第一区域和要形成漏极的半导体衬底的第二区域和第一掩模的至少一部分中的至少一个重叠; 通过使用第一和第二掩模蚀刻半导体衬底，从而在未被第一和第二掩模覆盖的半导体衬底的区域中形成凹陷部分; 在所述半导体衬底的凹陷部分中形成第二掺杂区域; 以及去除第一和第二掩模，并且至少在凹部的侧表面上形成包括第一绝缘膜，浮栅电极，第二绝缘膜和控制栅电极的栅结构，以及由第一绝缘膜， 面具。