公开(公告)号：US06184553B2

公开(公告)日：2001-02-06

申请号：US09325772

申请日：1999-06-04

申请人： Shinji Odanaka ,  Kaori Akamatsu ,  Junichi Kato ,  Atsushi Hori ,  Seiki Ogura

发明人： Shinji Odanaka ,  Kaori Akamatsu ,  Junichi Kato ,  Atsushi Hori ,  Seiki Ogura

IPC分类号： H07L27115

CPC分类号： H01L29/66825 ,  H01L21/28273 ,  H01L29/42324 ,  H01L29/7885

摘要： In a semiconductor substrate having a surface including a first surface region at a first level, a second surface region at a second level lower than the first level, and a step side region linking the first surface region and the second surface region together, a channel region has a triple structure. Thus, a high electric field is formed in a corner portion between the step side region and the second surface region and in the vicinity thereof. A high electric field is also formed in the first surface region. As a result, the efficiency, with which electrons are injected into a floating gate, is considerably increased.

公开(公告)号：US06051860A

公开(公告)日：2000-04-18

申请号：US8572

申请日：1998-01-16

申请人： Shinji Odanaka ,  Kaori Akamatsu ,  Junichi Kato ,  Atsushi Hori ,  Seiki Ogura

发明人： Shinji Odanaka ,  Kaori Akamatsu ,  Junichi Kato ,  Atsushi Hori ,  Seiki Ogura

IPC分类号： H01L21/8247 ,  H01L21/28 ,  H01L21/336 ,  H01L27/115 ,  H01L29/423 ,  H01L29/788 ,  H01L29/792 ,  H01L29/72

CPC分类号： H01L29/66825 ,  H01L21/28273 ,  H01L29/42324 ,  H01L29/7885

摘要： In a semiconductor substrate having a surface including a first surface region at a first level, a second surface region at a second level lower than the first level, and a step side region linking the first surface region and the second surface region together, a channel region has a triple structure. Thus, a high electric field is formed in a corner portion between the step side region and the second surface region and in the vicinity thereof. A high electric field is also formed in the first surface region. As a result, the efficiency, with which electrons are injected into a floating gate, is considerably increased.

摘要翻译： 在具有包括第一水平的第一表面区域的表面的半导体衬底中，具有低于第一水平的第二水平的第二表面区域和将第一表面区域和第二表面区域连接在一起的阶梯侧区域，通道 区域有三重结构。 因此，在台阶侧区域和第二表面区域之间的角部及其附近形成高电场。 在第一表面区域也形成高电场。 结果，电子注入浮栅的效率大大增加。

公开(公告)号：US06380585B1

公开(公告)日：2002-04-30

申请号：US09588308

申请日：2000-06-06

申请人： Shinji Odanaka ,  Kaori Akamatsu ,  Junichi Kato ,  Atsushi Hori ,  Seiki Ogura

发明人： Shinji Odanaka ,  Kaori Akamatsu ,  Junichi Kato ,  Atsushi Hori ,  Seiki Ogura

IPC分类号： H01L29788

CPC分类号： H01L29/66825 ,  H01L29/42324 ,  H01L29/7885

摘要： The nonvolatile semiconductor memory device of the present invention includes: a semiconductor substrate having a surface including a first surface region at a first level, a second surface region at a second level lower than the first level, and a step side region linking the first surface region and the second surface region together; a channel region formed in the first surface region of the semiconductor substrate; a source region and a drain region which are formed in the surface of the semiconductor substrate so as to interpose the channel region therebetween; a first insulating film formed on the surface of the semiconductor substrate; a floating gate formed on the first insulating film; a second insulating film formed on the floating gate; and a control gate which is capacitively coupled to the floating gate via the second insulating film. The drain region includes a low-concentration impurity layer which is formed in the second surface region and which has one end extending toward the step side region, and a high-concentration impurity layer which is connected to the low-concentration impurity layer and which is formed in a region distant from the channel region. As impurity concentration of the low-concentration impurity layer is lower than an impurity concentration of the high-concentration impurity layer. The floating gate covers the step side region and at least a part of the low-concentration impurity layer via the first insulating film.

摘要翻译： 本发明的非易失性半导体存储器件包括：半导体衬底，具有包括第一层的第一表面区域，低于第一层次的第二层的第二表面区域和将第一表面 区域和第二表面区域在一起; 形成在所述半导体衬底的所述第一表面区域中的沟道区; 源极区域和漏极区域，其形成在半导体衬底的表面中，以便在其间插入沟道区域; 形成在所述半导体衬底的表面上的第一绝缘膜; 形成在第一绝缘膜上的浮栅; 形成在浮动栅极上的第二绝缘膜; 以及通过第二绝缘膜电容耦合到浮动栅极的控制栅极。 漏区包括形成在第二表面区域中并且具有朝向台阶侧区域延伸的一端的低浓度杂质层和连接到低浓度杂质层的高浓度杂质层， 形成在远离通道区域的区域中。 由于低浓度杂质层的杂质浓度低于高浓度杂质层的杂质浓度。 浮置栅极经由第一绝缘膜覆盖台阶侧区域和至少一部分低浓度杂质层。

公开(公告)号：US06358799B2

公开(公告)日：2002-03-19

申请号：US09727536

申请日：2000-12-04

申请人： Shinji Odanaka ,  Kaori Akamatsu ,  Junichi Kato ,  Atsushi Hori ,  Seiki Ogura

发明人： Shinji Odanaka ,  Kaori Akamatsu ,  Junichi Kato ,  Atsushi Hori ,  Seiki Ogura

IPC分类号： H01L21336

CPC分类号： H01L29/66825 ,  H01L21/28273 ,  H01L29/42324 ,  H01L29/7885

摘要： In a semiconductor substrate having a surface including a first surface region at a first level, a second surface region at a second level lower than the first level, and a step side region linking the first surface region and the second surface region together, a channel region has a triple structure. Thus, a high electric field is formed in a corner portion between the step side region and the second surface region and in the vicinity thereof. A high electric field is also formed in the first surface region. As a result, the efficiency, with which electrons are injected into a floating gate, is considerably increased.

摘要翻译： 在具有包括第一水平的第一表面区域的表面的半导体衬底中，具有低于第一水平的第二水平的第二表面区域和将第一表面区域和第二表面区域连接在一起的阶梯侧区域，通道 区域有三重结构。 因此，在台阶侧区域和第二表面区域之间的角部及其附近形成高电场。 在第一表面区域也形成高电场。 结果，电子注入浮栅的效率大大增加。

公开(公告)号：US6121655A

公开(公告)日：2000-09-19

申请号：US848

申请日：1997-12-30

申请人： Shinji Odanaka ,  Kaori Akamatsu ,  Junichi Kato ,  Atsushi Hori ,  Seiki Ogura

发明人： Shinji Odanaka ,  Kaori Akamatsu ,  Junichi Kato ,  Atsushi Hori ,  Seiki Ogura

IPC分类号： G11C16/04 ,  H01L21/336 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/423 ,  H01L29/788 ,  H01L29/792 ,  H01L29/76

CPC分类号： H01L29/66825 ,  H01L29/42324 ,  H01L29/7885

摘要： The nonvolatile semiconductor memory device of the present invention includes: a semiconductor substrate having a surface including a first surface region at a first level, a second surface region at a second level lower than the first level, and a step side region linking the first surface region and the second surface region together; a channel region formed in the first surface region of the semiconductor substrate; a source region and a drain region which are formed in the surface of the semiconductor substrate so as to interpose the channel region therebetween; a first insulating film formed on the surface of the semiconductor substrate; a floating gate formed on the first insulating film; a second insulating film formed on the floating gate; and a control gate which is capacitively coupled to the floating gate via the second insulating film. The drain region includes a low-concentration impurity layer which is formed in the second surface region and which has one end extending toward the step side region, and a high-concentration impurity layer which is connected to the low-concentration impurity layer and which is formed in a region distant from the channel region. As impurity concentration of the low-concentration impurity layer is lower than an impurity concentration of the high-concentration impurity layer. The floating gate covers the step side region and at least a part of the low-concentration impurity layer via the first insulating film.

摘要翻译： 本发明的非易失性半导体存储器件包括：半导体衬底，具有包括第一层的第一表面区域，低于第一层次的第二层的第二表面区域和将第一表面 区域和第二表面区域在一起; 形成在所述半导体衬底的所述第一表面区域中的沟道区; 源极区域和漏极区域，其形成在半导体衬底的表面中，以便在其间插入沟道区域; 形成在所述半导体衬底的表面上的第一绝缘膜; 形成在第一绝缘膜上的浮栅; 形成在浮动栅极上的第二绝缘膜; 以及通过第二绝缘膜电容耦合到浮动栅极的控制栅极。 漏区包括形成在第二表面区域中并且具有朝向台阶侧区域延伸的一端的低浓度杂质层和连接到低浓度杂质层的高浓度杂质层， 形成在远离通道区域的区域中。 由于低浓度杂质层的杂质浓度低于高浓度杂质层的杂质浓度。 浮置栅极经由第一绝缘膜覆盖台阶侧区域和至少一部分低浓度杂质层。

公开(公告)号：US6147379A

公开(公告)日：2000-11-14

申请号：US58803

申请日：1998-04-13

申请人： Atsushi Hori ,  Junichi Kato ,  Shinji Odanaka ,  Seiki Ogura ,  Kaori Akamatsu

发明人： Atsushi Hori ,  Junichi Kato ,  Shinji Odanaka ,  Seiki Ogura ,  Kaori Akamatsu

IPC分类号： H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

CPC分类号： H01L29/7885

摘要： The nonvolatile semiconductor memory device of the invention includes: a semiconductor substrate having a surface including a first surface region at a first level, a second surface region at a second level lower than the first level, and a step side region linking the first and second surface regions; a channel region formed in the first surface region of the semiconductor substrate; a source region and a drain region which are formed in the surface of the semiconductor substrate so as to interpose the channel region therebetween; a first insulating film formed on the surface of the semiconductor substrate; a floating gate formed on the first insulating film; and a control gate capacitively coupled to the floating gate via a second insulating film. The first surface region is an upper surface of an epitaxially grown layer formed on the second surface region. The drain region includes: a low-concentration impurity layer formed in the second surface region and having one end extending toward the step side region; and a high-concentration impurity layer connected to the low-concentration impurity layer and formed in a region distant from the channel region. An impurity concentration of the low-concentration impurity layer is lower than that of the high-concentration impurity layer. The floating gate covers the step side region and at least a part of the low-concentration impurity layer via the first insulating film.

摘要翻译： 本发明的非易失性半导体存储器件包括：半导体衬底，具有包括第一电平的第一表面区域，低于第一电平的第二电平的第二表面区域和连接第一和第二电极的台阶侧区域的表面 表面区域 形成在所述半导体衬底的所述第一表面区域中的沟道区; 源极区域和漏极区域，其形成在半导体衬底的表面中，以便在其间插入沟道区域; 形成在所述半导体衬底的表面上的第一绝缘膜; 形成在第一绝缘膜上的浮栅; 以及经由第二绝缘膜电容耦合到浮置栅极的控制栅极。 第一表面区域是形成在第二表面区域上的外延生长层的上表面。 漏极区域包括：形成在第二表面区域中并且具有朝向台阶侧区域延伸的一端的低浓度杂质层; 以及连接到低浓度杂质层并形成在远离沟道区的区域中的高浓度杂质层。 低浓度杂质层的杂质浓度低于高浓度杂质层的杂质浓度。 浮置栅极经由第一绝缘膜覆盖台阶侧区域和至少一部分低浓度杂质层。

公开(公告)号：US06312981B1

公开(公告)日：2001-11-06

申请号：US09511045

申请日：2000-02-23

申请人： Kaori Akamatsu ,  Shinji Odanaka ,  Hiroyuki Umimoto

发明人： Kaori Akamatsu ,  Shinji Odanaka ,  Hiroyuki Umimoto

IPC分类号： H01L218238

CPC分类号： H01L21/28185 ,  H01L21/2652 ,  H01L21/28211 ,  H01L21/324 ,  H01L21/74 ,  H01L21/823807 ,  H01L21/823892 ,  H01L29/105

摘要： A method for producing a semiconductor device includes the steps of: forming an impurity diffusion layer for controlling a threshold voltage by ion implantation; and conducting a high-temperature rapid heat treatment for recovering crystal defects generated by the ion implantation. More specifically, treatment conditions for the high-temperature rapid heat treatment are set in such a manner that interstitial atoms causing the crystal defects are diffused, and impurities in the impurity diffusion layer are not diffused. For example, the high-temperature rapid heat treatment is conducted in a temperature range of about 900° C. to about 1100° C.

公开(公告)号：US06251718B1

公开(公告)日：2001-06-26

申请号：US09011891

申请日：1998-02-23

申请人： Kaori Akamatsu ,  Shinji Odanaka ,  Hiroyuki Umimoto

发明人： Kaori Akamatsu ,  Shinji Odanaka ,  Hiroyuki Umimoto

IPC分类号： H01L218238

CPC分类号： H01L21/28185 ,  H01L21/2652 ,  H01L21/28211 ,  H01L21/324 ,  H01L21/74 ,  H01L21/823807 ,  H01L21/823892 ,  H01L29/105

摘要： A method for producing a semiconductor device includes the steps of: forming an impurity diffusion layer for controlling a threshold voltage by ion implantation; and conducting a high-temperature rapid heat treatment for recovering crystal defects generated by the ion implantation. More specifically, treatment conditions for the high-temperature rapid heat treatment are set in such a manner that interstitial atoms causing the crystal defects are diffused, and impurities in the impurity diffusion layer are not diffused. For example, the high-temperature rapid heat treatment is conducted in a temperature range of about 900° C. to about 1100° C.

摘要翻译： 一种制造半导体器件的方法包括以下步骤：通过离子注入形成用于控制阈值电压的杂质扩散层; 并进行高温快速热处理，以回收由离子注入产生的晶体缺陷。 更具体地说，高温快速热处理的处理条件被设定为使得晶体缺陷引起的间隙原子扩散，杂质扩散层中的杂质不扩散。 例如，高温快速热处理在约900℃至约1100℃的温度范围内进行。

公开(公告)号：US07893501B2

公开(公告)日：2011-02-22

申请号：US12170191

申请日：2008-07-09

申请人： Masafumi Tsutsui ,  Hiroyuki Umimoto ,  Kaori Akamatsu

发明人： Masafumi Tsutsui ,  Hiroyuki Umimoto ,  Kaori Akamatsu

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L29/7843 ,  H01L21/823807 ,  H01L21/823814 ,  H01L27/092

摘要： A semiconductor device includes a first-type internal stress film formed of a silicon oxide film over source/drain regions of an nMISFET and a second-type internal stress film formed of a TEOS film over source/drain regions of a pMISFET. In a channel region of the nMISFET, a tensile stress is generated in the direction of movement of electrons due to the first-type internal stress film, so that the mobility of electrons is increased. In a channel region of the pMISFET, a compressive stress is generated in the direction of movement of holes due to the second-type internal stress film, so that the mobility of holes is increased.

摘要翻译： 半导体器件包括由nMISFET的源极/漏极区域上的氧化硅膜形成的第一型内部应力膜和在pMISFET的源极/漏极区域上由TEOS膜形成的第二类型内部应力膜。 在nMISFET的沟道区域中，由于第一型内应力膜，电子的移动方向产生拉伸应力，使得电子的迁移率增加。 在pMISFET的沟道区域中，由于第二类型的内部应力膜，在孔的移动方向上产生压缩应力，使得孔的迁移率增加。

公开(公告)号：US07417289B2

公开(公告)日：2008-08-26

申请号：US11730988

申请日：2007-04-05

申请人： Masafumi Tsutsui ,  Hiroyuki Umimoto ,  Kaori Akamatsu

发明人： Masafumi Tsutsui ,  Hiroyuki Umimoto ,  Kaori Akamatsu

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L29/7843 ,  H01L21/823807 ,  H01L21/823814 ,  H01L27/092

摘要： A semiconductor device includes a first-type internal stress film formed of a silicon oxide film over source/drain regions of an nMISFET and a second-type internal stress film formed of a TEOS film over source/drain regions of a pMISFET. In a channel region of the nMISFET, a tensile stress is generated in the direction of movement of electrons due to the first-type internal stress film, so that the mobility of electrons is increased. In a channel region of the pMISFET, a compressive stress is generated in the direction of movement of holes due to the second-type internal stress film, so that the mobility of holes is increased.

摘要翻译： 半导体器件包括由nMISFET的源极/漏极区域上的氧化硅膜形成的第一型内部应力膜和在pMISFET的源极/漏极区域上由TEOS膜形成的第二类型内部应力膜。 在nMISFET的沟道区域中，由于第一型内应力膜，电子的移动方向产生拉伸应力，使得电子的迁移率增加。 在pMISFET的沟道区域中，由于第二类型的内部应力膜，在孔的移动方向上产生压缩应力，使得孔的迁移率增加。