公开(公告)号：US06889240B2

公开(公告)日：2005-05-03

申请号：US10694771

申请日：2003-10-29

申请人： Atsushi Kiuchi ,  Yuji Hatano ,  Toru Baji ,  Koki Noguchi ,  Yasushi Akao ,  Shiro Baba

发明人： Atsushi Kiuchi ,  Yuji Hatano ,  Toru Baji ,  Koki Noguchi ,  Yasushi Akao ,  Shiro Baba

IPC分类号： G06F5/01 ,  G06F7/00 ,  G06F7/76 ,  G06F9/302 ,  G06F9/312 ,  G06F9/34 ,  G06F9/38 ,  G06F15/78 ,  G06F17/10 ,  G06F7/38

CPC分类号： G06F9/30014 ,  G06F9/30036 ,  G06F9/30043

摘要： In microcomputers and digital signal processors in which a central processing unit for controlling the entire system and a digital signal processing unit having a product sum function required to process digital signals efficiently are mounted on one and the same chip, an increase in the number of processing steps caused by differing types of data handled by the calculators is prevented, thereby enhancing the efficiency of the digital signal processing.

摘要翻译： 在其中用于控制整个系统的中央处理单元和具有有效处理数字信号所需的乘积和功能的数字信号处理单元的微型计算机和数字信号处理单元安装在同一芯片上，处理次数的增加 防止由计算器处理的不同类型的数据引起的步骤，从而提高数字信号处理的效率。

公开(公告)号：US5884092A

公开(公告)日：1999-03-16

申请号：US725481

申请日：1996-10-04

申请人： Atsushi Kiuchi ,  Yuji Hatano ,  Toru Baji ,  Koki Noguchi ,  Yasushi Akao ,  Shiro Baba

发明人： Atsushi Kiuchi ,  Yuji Hatano ,  Toru Baji ,  Koki Noguchi ,  Yasushi Akao ,  Shiro Baba

IPC分类号： G06F5/01 ,  G06F7/00 ,  G06F7/76 ,  G06F9/302 ,  G06F9/312 ,  G06F9/34 ,  G06F9/38 ,  G06F15/78 ,  G06F17/10 ,  G06F15/00

CPC分类号： G06F9/30014 ,  G06F9/30036 ,  G06F9/30043

摘要： In microcomputers and digital signal processors in which a central processing unit for controlling the entire system and a digital signal processing unit having a product sum function required to process digital signals efficiently are mounted on one and the same chippthis invention prevents an increase in the number of processing steps caused by differing types of data handled by the calculators, thereby enhancing the efficiency of the digital signal processing.The digital signal processing unit is made a calculation unit that handles fixed-point data, and an instruction calling for execution of a fixed-point data calculation is provided separately from the conventional integer calculation instruction. When, in the data transfer between the digital signal processing unit and memories or external circuits, data shorter in bit length than the calculation precision is transferred, the calculation unit has a function to input and output data to and from the higher-order side of the register in which the data is stored and the fixed point data transfer instruction is provided separately from the conventional integer data transfer instruction.This invention can eliminate additional correction processing necessitated when the integer data processing unit is made to execute the digitalsignal processing.

摘要翻译： 在其中用于控制整个系统的中央处理单元和具有有效处理数字信号所需的乘积和功能的数字信号处理单元的微型计算机和数字信号处理器被安装在同一个发明中，防止了数量的增加 由计算器处理的不同类型的数据引起的处理步骤，从而提高数字信号处理的效率。 数字信号处理单元是处理定点数据的计算单元，并且与常规整数计算指令分开提供调用执行定点数据计算的指令。 当在数字信号处理单元和存储器或外部电路之间的数据传送中，位长度比传送计算精度更短的数据时，计算单元具​​有向数据信号处理单元和存储器或外部电路的高阶侧输入和输出数据的功能， 存储数据的寄存器和固定点数据传送指令与传统的整数数据传送指令分开提供。 本发明可以消除当整数数据处理单元执行数字信号处理时所需的附加校正处理。

公开(公告)号：US06668266B2

公开(公告)日：2003-12-23

申请号：US09973734

申请日：2001-10-11

申请人： Atsushi Kiuchi ,  Yuji Hatano ,  Toru Baji ,  Koki Noguchi ,  Yasushi Akao ,  Shiro Baba

发明人： Atsushi Kiuchi ,  Yuji Hatano ,  Toru Baji ,  Koki Noguchi ,  Yasushi Akao ,  Shiro Baba

IPC分类号： G06F738

CPC分类号： G06F9/30014 ,  G06F9/30036 ,  G06F9/30043

摘要： In microcomputers and digital signal processors in which a central processing unit for controlling the entire system and a digital signal processing unit having a product sum function required to process digital signals efficiently are mounted on one and the same chip, an increase in the number of processing steps caused by differing types of data handled by the calculators is prevented, thereby enhancing the efficiency of the digital signal processing.

摘要翻译： 在其中用于控制整个系统的中央处理单元和具有有效处理数字信号所需的乘积和功能的数字信号处理单元的微型计算机和数字信号处理单元安装在同一芯片上，处理次数的增加 防止由计算器处理的不同类型的数据引起的步骤，从而提高数字信号处理的效率。

公开(公告)号：US06434690B1

公开(公告)日：2002-08-13

申请号：US09229147

申请日：1999-01-11

申请人： Hiroshi Ohsuga ,  Atsushi Kiuchi ,  Hironobu Hasegawa ,  Toru Baji ,  Koki Noguchi ,  Yasushi Akao ,  Shiro Baba

发明人： Hiroshi Ohsuga ,  Atsushi Kiuchi ,  Hironobu Hasegawa ,  Toru Baji ,  Koki Noguchi ,  Yasushi Akao ,  Shiro Baba

IPC分类号： G06F1576

CPC分类号： G06F9/3893 ,  G06F9/3001 ,  G06F9/30043 ,  G06F9/3013 ,  G06F9/30145 ,  G06F9/30149 ,  G06F9/30167 ,  G06F9/3017 ,  G06F9/345 ,  G06F9/3552 ,  G06F9/3802 ,  G06F9/3814 ,  G06F9/3824 ,  G06F9/3877 ,  G06F15/7817

摘要： A built-in memory is divided into the following two types: first memories 5 and 7 and second memories 4 and 6, and made accessible in parallel by third buses XAB and XDB and second buses YAB and YDB respectively. Thereby, a CPU core 2 can simultaneously transfer two data values from the built-in memory to a DSP engine 3. Moreover, the third buses XAB and XDB and the second buses YAB and YDB are also separate from first buses IAB and IDB to be externally interfaced and the CPU core 2 can access an external memory in parallel with the access to the second memories 4 and 6 and the first memories 5 and

摘要翻译： 内置存储器被分为以下两种类型：第一存储器5和7以及第二存储器4和6，并且分别由第三总线XAB和XDB以及第二总线YAB和YDB并行访问。 因此，CPU核心2可以同时将两个数据值从内置存储器传送到DSP引擎3.此外，第三总线XAB和XDB以及第二总线YAB和YDB也与第一总线IAB和IDB分离成为 外部接口并且CPU核心2可以与访问第二存储器4和6以及第一存储器5和

公开(公告)号：US06405302B1

公开(公告)日：2002-06-11

申请号：US09291910

申请日：1999-04-14

申请人： Hiroshi Ohsuga ,  Atsushi Kiuchi ,  Hironobu Hasegawa ,  Toru Baji ,  Koki Noguchi ,  Yasushi Akao ,  Shiro Baba

发明人： Hiroshi Ohsuga ,  Atsushi Kiuchi ,  Hironobu Hasegawa ,  Toru Baji ,  Koki Noguchi ,  Yasushi Akao ,  Shiro Baba

IPC分类号： G06F1340

CPC分类号： G06F9/3893 ,  G06F9/3001 ,  G06F9/30043 ,  G06F9/3013 ,  G06F9/30145 ,  G06F9/30149 ,  G06F9/30167 ,  G06F9/3017 ,  G06F9/345 ,  G06F9/3552 ,  G06F9/3802 ,  G06F9/3814 ,  G06F9/3824 ,  G06F9/3877 ,  G06F15/7817

摘要： A built-in memory is divided into the following two types: first memories 5 and 7 and second memories 4 and 6, and made accessible in parallel by third buses XAB and XDB and second buses YAB and YDB respectively. Thereby, a CPU core 2 can simultaneously transfer two data values from the built-in memory to a DSP engine 3. Moreover, the third buses XAB and XDB and the second buses YAB and YDB are also separate from first buses IAB and IDB to be externally interfaced and the CPU core 2 can access an external memory in parallel with the access to the second memories 4 and 6 and the first memories 5 and 7.

公开(公告)号：US07069423B2

公开(公告)日：2006-06-27

申请号：US10201402

申请日：2002-07-22

申请人： Hiroshi Ohsuga ,  Atsushi Kiuchi ,  Hironobu Hasegawa ,  Toru Baji ,  Koki Noguchi ,  Yasushi Akao ,  Shiro Baba

发明人： Hiroshi Ohsuga ,  Atsushi Kiuchi ,  Hironobu Hasegawa ,  Toru Baji ,  Koki Noguchi ,  Yasushi Akao ,  Shiro Baba

IPC分类号： G06F9/30

CPC分类号： G06F9/3893 ,  G06F9/3001 ,  G06F9/30043 ,  G06F9/3013 ,  G06F9/30145 ,  G06F9/30149 ,  G06F9/30167 ,  G06F9/3017 ,  G06F9/345 ,  G06F9/3552 ,  G06F9/3802 ,  G06F9/3814 ,  G06F9/3824 ,  G06F9/3877 ,  G06F15/7817

摘要： A built-in memory is divided into the following two types: first memories 5 and 7 and second memories 4 and 6, and made accessible in parallel by third buses XAB and XDB and second buses YAB and YDB respectively. Thereby, a CPU core 2 can simultaneously transfer two data values from the built-in memory to a DSP engine 3. Moreover, the third buses XAB and XDB and the second buses YAB and YDB are also separate from first buses IAB and IDB to be externally interfaced and the CPU core 2 can access an external memory in parallel with the access to the second memories 4 and 6 and the first memories 5 and 7.

公开(公告)号：US07363466B2

公开(公告)日：2008-04-22

申请号：US11354622

申请日：2006-02-14

申请人： Hiroshi Ohsuga ,  Atsushi Kiuchi ,  Hironobu Hasegawa ,  Toru Baji ,  Koki Noguchi ,  Yasushi Akao ,  Shiro Baba

发明人： Hiroshi Ohsuga ,  Atsushi Kiuchi ,  Hironobu Hasegawa ,  Toru Baji ,  Koki Noguchi ,  Yasushi Akao ,  Shiro Baba

IPC分类号： G06F15/76 ,  G06F9/00 ,  G06F13/00

CPC分类号： G06F9/3893 ,  G06F9/3001 ,  G06F9/30043 ,  G06F9/3013 ,  G06F9/30145 ,  G06F9/30149 ,  G06F9/30167 ,  G06F9/3017 ,  G06F9/345 ,  G06F9/3552 ,  G06F9/3802 ,  G06F9/3814 ,  G06F9/3824 ,  G06F9/3877 ,  G06F15/7817

摘要： A built-in memory is divided into the following two types: first memories 5 and 7 and second memories 4 and 6, and made accessible in parallel by third buses XAB and XDB and second buses YAB and YDB respectively. Thereby, a CPU core 2 can simultaneously transfer two data values from the built-in memory to a DSP engine 3. Moreover, the third buses XAB and XDB and the second buses YAB and YDB are also separate from first buses IAB and IDB to be externally interfaced and the CPU core 2 can access an external memory in parallel with the access to the second memories 4 and 6 and the first memories 5 and 7.

摘要翻译： 内置存储器被分为以下两种类型：第一存储器5和7以及第二存储器4和6，并且分别由第三总线XAB和XDB以及第二总线YAB和YDB并行访问。 由此，CPU核心2可以将来自内置存储器的两个数据值同时传送到DSP引擎3。 此外，第三总线XAB和XDB以及第二总线YAB和YDB也与要外部接口的第一总线IAB和IDB分开，并且CPU核心2可以与访问第二存储器4和6并行地访问外部存储器 和第一存储器5和7。

公开(公告)号：US07558944B2

公开(公告)日：2009-07-07

申请号：US12075131

申请日：2008-03-07

申请人： Hiroshi Ohsuga ,  Atsushi Kiuchi ,  Hironobu Hasegawa ,  Toru Baji ,  Koki Noguchi ,  Yasushi Akao ,  Shiro Baba

发明人： Hiroshi Ohsuga ,  Atsushi Kiuchi ,  Hironobu Hasegawa ,  Toru Baji ,  Koki Noguchi ,  Yasushi Akao ,  Shiro Baba

IPC分类号： G06F15/76 ,  G06F13/00 ,  G06F9/26

CPC分类号： G06F9/3893 ,  G06F9/3001 ,  G06F9/30043 ,  G06F9/3013 ,  G06F9/30145 ,  G06F9/30149 ,  G06F9/30167 ,  G06F9/3017 ,  G06F9/345 ,  G06F9/3552 ,  G06F9/3802 ,  G06F9/3814 ,  G06F9/3824 ,  G06F9/3877 ,  G06F15/7817

摘要： A built-in memory is divided into the following two types: first memories 5 and 7 and second memories 4 and 6, and made accessible in parallel by third buses XAB and XDB and second buses YAB and YDB respectively. Thereby, a CPU core 2 can simultaneously transfer two data values from the built-in memory to a DSP engine 3. Moreover, the third buses XAB and XDB and the second buses YAB and YDB are also separate from first buses IAB and IDB to be externally interfaced and the CPU core 2 can access an external memory in parallel with the access to the second memories 4 and 6 and the first memories 5 and 7.

公开(公告)号：US5867726A

公开(公告)日：1999-02-02

申请号：US630320

申请日：1996-04-10

申请人： Hiroshi Ohsuga ,  Atsushi Kiuchi ,  Hironobu Hasegawa ,  Toru Baji ,  Koki Noguchi ,  Yasushi Akao ,  Shiro Baba

发明人： Hiroshi Ohsuga ,  Atsushi Kiuchi ,  Hironobu Hasegawa ,  Toru Baji ,  Koki Noguchi ,  Yasushi Akao ,  Shiro Baba

IPC分类号： G06F12/06 ,  G06F9/30 ,  G06F9/34 ,  G06F9/355 ,  G06F9/38 ,  G06F12/00 ,  G06F13/16 ,  G06F15/76 ,  G06F15/78

CPC分类号： G06F9/3893 ,  G06F15/7817 ,  G06F9/3001 ,  G06F9/30043 ,  G06F9/3013 ,  G06F9/30145 ,  G06F9/30149 ,  G06F9/30167 ,  G06F9/3017 ,  G06F9/345 ,  G06F9/3552 ,  G06F9/3802 ,  G06F9/3814 ,  G06F9/3824 ,  G06F9/3877

摘要： A built-in memory is divided into the following two types: first memories 5 and 7 and second memories 4 and 6, and made accessible in parallel by third buses XAB and XDB and second buses YAB and YDB respectively. Thereby, a CPU core 2 can simultaneously transfer two data values from the built-in memory to a DSP engine 3. Moreover, the third buses XAB and XDB and the second buses YAB and YDB are also separate from first buses IAB and IDB to be externally interfaced and the CPU core 2 can access an external memory in parallel with the access to the second memories 4 and 6 and the first memories 5 and 7.

公开(公告)号：US20080294873A1

公开(公告)日：2008-11-27

申请号：US12075131

申请日：2008-03-07

申请人： Hiroshi Ohsuga ,  Atsushi Kiuchi ,  Hironobu Hasegawa ,  Toru Baji ,  Koki Noguchi ,  Yasushi Akao ,  Shiro Baba

发明人： Hiroshi Ohsuga ,  Atsushi Kiuchi ,  Hironobu Hasegawa ,  Toru Baji ,  Koki Noguchi ,  Yasushi Akao ,  Shiro Baba

IPC分类号： G06F15/76 ,  G06F9/30

CPC分类号： G06F9/3893 ,  G06F9/3001 ,  G06F9/30043 ,  G06F9/3013 ,  G06F9/30145 ,  G06F9/30149 ,  G06F9/30167 ,  G06F9/3017 ,  G06F9/345 ,  G06F9/3552 ,  G06F9/3802 ,  G06F9/3814 ,  G06F9/3824 ,  G06F9/3877 ,  G06F15/7817

摘要： A built-in memory is divided into the following two types: first memories 5 and 7 and second memories 4 and 6, and made accessible in parallel by third buses XAB and XDB and second buses YAB and YDB respectively. Thereby, a CPU core 2 can simultaneously transfer two data values from the built-in memory to a DSP engine 3. Moreover, the third buses XAB and XDB and the second buses YAB and YDB are also separate from first buses IAB and IDB to be externally interfaced and the CPU core 2 can access an external memory in parallel with the access to the second memories 4 and 6 and the first memories 5 and 7.

摘要翻译： 内置存储器被分为以下两种类型：第一存储器5和7以及第二存储器4和6，并且分别由第三总线XAB和XDB以及第二总线YAB和YDB并行访问。 因此，CPU核心2可以同时将两个数据值从内置存储器传送到DSP引擎3.此外，第三总线XAB和XDB以及第二总线YAB和YDB也与第一总线IAB和IDB分离成为 外部接口并且CPU核心2可以与对第二存储器4和6以及第一存储器5和7的访问并行地访问外部存储器。