公开(公告)号：US08090398B2

公开(公告)日：2012-01-03

申请号：US12112968

申请日：2008-04-30

申请人： Tetsuya Nakagawa ,  Yuji Hatano ,  Yasuhiro Sagesaka ,  Toru Baji ,  Koki Noguchi

发明人： Tetsuya Nakagawa ,  Yuji Hatano ,  Yasuhiro Sagesaka ,  Toru Baji ,  Koki Noguchi

IPC分类号： H04M1/00

CPC分类号： G06F9/3885 ,  G06F1/3203 ,  G06F15/7807

摘要： A low cost, a low power consumption and a small size are three very important factors for a mobile communication terminal. A great problem is posed by the conventional technique using a DSP and a CPU independent of each other which requires two external memory systems. Also, two peripheral units are required for data input and output of the DSP and CPU. As a result, an extraneous communication overhead occurs between the DSP and the CPU. The invention realizes a mobile communication terminal system by a DSP/CPU integrated chip comprising a DSP/CPU core (500) integrated as a single bus master, an integrated external bus interface (606) and an integrated peripheral circuit interface. The memory systems and the peripheral circuits of the DSP and the CPU can thus be integrated to realize a mobile communication terminal system low in cost and power consumption and small in size.

摘要翻译： 低成本，低功耗和小尺寸是移动通信终端的三个非常重要的因素。 使用DSP和独立于彼此的CPU的传统技术提出了一个很大的问题，需要两个外部存储器系统。 此外，DSP和CPU的数据输入和输出需要两个外设单元。 因此，DSP和CPU之间会发生无关的通信开销。 本发明通过DSP / CPU集成芯片实现移动通信终端系统，其包括集成为单总线主机的DSP / CPU核心（500），集成外部总线接口（606）和集成外围电路接口。 因此，DSP和CPU的存储器系统和外围电路可以被集成以实现低成本和功耗以及体积小的移动通信终端系统。

公开(公告)号：US07558944B2

公开(公告)日：2009-07-07

申请号：US12075131

申请日：2008-03-07

申请人： Hiroshi Ohsuga ,  Atsushi Kiuchi ,  Hironobu Hasegawa ,  Toru Baji ,  Koki Noguchi ,  Yasushi Akao ,  Shiro Baba

发明人： Hiroshi Ohsuga ,  Atsushi Kiuchi ,  Hironobu Hasegawa ,  Toru Baji ,  Koki Noguchi ,  Yasushi Akao ,  Shiro Baba

IPC分类号： G06F15/76 ,  G06F13/00 ,  G06F9/26

CPC分类号： G06F9/3893 ,  G06F9/3001 ,  G06F9/30043 ,  G06F9/3013 ,  G06F9/30145 ,  G06F9/30149 ,  G06F9/30167 ,  G06F9/3017 ,  G06F9/345 ,  G06F9/3552 ,  G06F9/3802 ,  G06F9/3814 ,  G06F9/3824 ,  G06F9/3877 ,  G06F15/7817

摘要： A built-in memory is divided into the following two types: first memories 5 and 7 and second memories 4 and 6, and made accessible in parallel by third buses XAB and XDB and second buses YAB and YDB respectively. Thereby, a CPU core 2 can simultaneously transfer two data values from the built-in memory to a DSP engine 3. Moreover, the third buses XAB and XDB and the second buses YAB and YDB are also separate from first buses IAB and IDB to be externally interfaced and the CPU core 2 can access an external memory in parallel with the access to the second memories 4 and 6 and the first memories 5 and 7.

公开(公告)号：US06810454B2

公开(公告)日：2004-10-26

申请号：US10337729

申请日：2003-01-08

申请人： Nobukazu Kondo ,  Ikuya Kawasaki ,  Koki Noguchi

发明人： Nobukazu Kondo ,  Ikuya Kawasaki ,  Koki Noguchi

IPC分类号： G06F1300

CPC分类号： G06F13/4059 ,  Y02D10/14 ,  Y02D10/151

摘要： An information processing apparatus includes a master module serving as a transfer source, a slave module serving as a transfer destination, a bus of a source clock synchronous system, and a means for transferring a signal based upon a protocol of an acknowledge type from the slave module to the master module via the bus of the source clock synchronous system. In the information processor, the signals of the acknowledge type are also transferred in the source clock synchronous system by using a source clock signal dedicated to signals of the acknowledge type. Therefore, it is prevented that the master side fails in acquiring signals of the acknowledge type from the slave side, and the reliability of the source clock synchronous bus and the data efficiency can be improved.

摘要翻译： 信息处理装置包括：作为传送源的主模块，用作传送目的地的从模块，源时钟同步系统的总线，以及用于基于来自从设备的确认类型的协议传送信号的装置 通过源时钟同步系统的总线模块到主模块。 在信息处理器中，确认类型的信号也通过使用专用于确认类型的信号的源时钟信号在源时钟同步系统中传送。 因此，防止主机侧从从机侧获取确认类型的信号失败，并且可以提高源时钟同步总线的可靠性和数据效率。

公开(公告)号：US06370665B1

公开(公告)日：2002-04-09

申请号：US09627007

申请日：2000-07-27

申请人： Koki Noguchi

发明人： Koki Noguchi

IPC分类号： G01R3128

CPC分类号： G01R31/318544

摘要： Disclosed herein are a semiconductor integrated circuit and a recording medium wherein the amount of test data inputted from and outputted to the outside to test a plurality of circuit modules and the amount of test result data are reduced and a test time interval is shortened. When each of tested circuits is tested, test control information is externally inputted to a test interface circuit, and test control information is set to each of scan registers of circuit modules to be tested, through a test signal chain. When an instruction for a test operation is given to each of test control circuits through a control terminal, a test circuit allows the tested circuits to be tested based on the test control information on a parallel basis. Test results are read into the test interface circuit from the scan registers through the test signal chain, followed by output to the outside. The test operations for the circuit modules can be parallelized and the test interface circuit can be shared between the respective circuit modules.

摘要翻译： 这里公开了一种半导体集成电路和记录介质，其中从外部输入并输出到测试多个电路模块的测试数据量和测试结果数据量减少，并且测试时间间隔缩短。 当测试每个测试电路时，测试控制信息被外部输入到测试接口电路，并且测试控制信息通过测试信号链设置到要测试的电路模块的每个扫描寄存器。 当通过控制终端向每个测试控制电路提供测试操作的指令时，测试电路允许测试电路基于并行的测试控制信息进行测试。 测试结果通过测试信号链从扫描寄存器读入测试接口电路，然后输出到外部。 电路模块的测试操作可以并行化，并且可以在各个电路模块之间共享测试接口电路。

公开(公告)号：US5884092A

公开(公告)日：1999-03-16

申请号：US725481

申请日：1996-10-04

申请人： Atsushi Kiuchi ,  Yuji Hatano ,  Toru Baji ,  Koki Noguchi ,  Yasushi Akao ,  Shiro Baba

发明人： Atsushi Kiuchi ,  Yuji Hatano ,  Toru Baji ,  Koki Noguchi ,  Yasushi Akao ,  Shiro Baba

IPC分类号： G06F5/01 ,  G06F7/00 ,  G06F7/76 ,  G06F9/302 ,  G06F9/312 ,  G06F9/34 ,  G06F9/38 ,  G06F15/78 ,  G06F17/10 ,  G06F15/00

CPC分类号： G06F9/30014 ,  G06F9/30036 ,  G06F9/30043

摘要： In microcomputers and digital signal processors in which a central processing unit for controlling the entire system and a digital signal processing unit having a product sum function required to process digital signals efficiently are mounted on one and the same chippthis invention prevents an increase in the number of processing steps caused by differing types of data handled by the calculators, thereby enhancing the efficiency of the digital signal processing.The digital signal processing unit is made a calculation unit that handles fixed-point data, and an instruction calling for execution of a fixed-point data calculation is provided separately from the conventional integer calculation instruction. When, in the data transfer between the digital signal processing unit and memories or external circuits, data shorter in bit length than the calculation precision is transferred, the calculation unit has a function to input and output data to and from the higher-order side of the register in which the data is stored and the fixed point data transfer instruction is provided separately from the conventional integer data transfer instruction.This invention can eliminate additional correction processing necessitated when the integer data processing unit is made to execute the digitalsignal processing.

摘要翻译： 在其中用于控制整个系统的中央处理单元和具有有效处理数字信号所需的乘积和功能的数字信号处理单元的微型计算机和数字信号处理器被安装在同一个发明中，防止了数量的增加 由计算器处理的不同类型的数据引起的处理步骤，从而提高数字信号处理的效率。 数字信号处理单元是处理定点数据的计算单元，并且与常规整数计算指令分开提供调用执行定点数据计算的指令。 当在数字信号处理单元和存储器或外部电路之间的数据传送中，位长度比传送计算精度更短的数据时，计算单元具​​有向数据信号处理单元和存储器或外部电路的高阶侧输入和输出数据的功能， 存储数据的寄存器和固定点数据传送指令与传统的整数数据传送指令分开提供。 本发明可以消除当整数数据处理单元执行数字信号处理时所需的附加校正处理。

公开(公告)号：US5867726A

公开(公告)日：1999-02-02

申请号：US630320

申请日：1996-04-10

申请人： Hiroshi Ohsuga ,  Atsushi Kiuchi ,  Hironobu Hasegawa ,  Toru Baji ,  Koki Noguchi ,  Yasushi Akao ,  Shiro Baba

发明人： Hiroshi Ohsuga ,  Atsushi Kiuchi ,  Hironobu Hasegawa ,  Toru Baji ,  Koki Noguchi ,  Yasushi Akao ,  Shiro Baba

IPC分类号： G06F12/06 ,  G06F9/30 ,  G06F9/34 ,  G06F9/355 ,  G06F9/38 ,  G06F12/00 ,  G06F13/16 ,  G06F15/76 ,  G06F15/78

CPC分类号： G06F9/3893 ,  G06F15/7817 ,  G06F9/3001 ,  G06F9/30043 ,  G06F9/3013 ,  G06F9/30145 ,  G06F9/30149 ,  G06F9/30167 ,  G06F9/3017 ,  G06F9/345 ,  G06F9/3552 ,  G06F9/3802 ,  G06F9/3814 ,  G06F9/3824 ,  G06F9/3877

摘要： A built-in memory is divided into the following two types: first memories 5 and 7 and second memories 4 and 6, and made accessible in parallel by third buses XAB and XDB and second buses YAB and YDB respectively. Thereby, a CPU core 2 can simultaneously transfer two data values from the built-in memory to a DSP engine 3. Moreover, the third buses XAB and XDB and the second buses YAB and YDB are also separate from first buses IAB and IDB to be externally interfaced and the CPU core 2 can access an external memory in parallel with the access to the second memories 4 and 6 and the first memories 5 and 7.

公开(公告)号：US07138722B2

公开(公告)日：2006-11-21

申请号：US11057495

申请日：2005-02-15

申请人： Toshio Miyamoto ,  Asao Nishimura ,  Koki Noguchi ,  Satoshi Michishita ,  Masashi Horiguchi ,  Masaharu Kubo ,  Kazuyoshi Shiba

发明人： Toshio Miyamoto ,  Asao Nishimura ,  Koki Noguchi ,  Satoshi Michishita ,  Masashi Horiguchi ,  Masaharu Kubo ,  Kazuyoshi Shiba

IPC分类号： H01L23/48

CPC分类号： H01L24/50 ,  H01L23/49572 ,  H01L23/49816 ,  H01L24/06 ,  H01L24/45 ,  H01L24/48 ,  H01L25/0657 ,  H01L25/105 ,  H01L27/10897 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/06136 ,  H01L2224/16245 ,  H01L2224/451 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2225/1029 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2225/107 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01021 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01055 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/12033 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15311 ,  H01L2924/15312 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/3011 ,  H01L2924/3511 ,  H01L2924/00015 ,  H01L2224/05599 ,  H01L2924/00 ,  H01L2924/00012

摘要： Described herein is a stacked package according to the present invention, wherein a plurality of tape carriers which seal semiconductor chips, are multilayered in upward and downward directions. In the stacked package, one ends of leads formed over the whole surfaces of each tape carrier are electrically connected to their corresponding connecting terminals of the semiconductor chip. Other ends of the leads are electrically connected to their corresponding through holes defined in the tape carrier. Connecting terminals common to the plurality of semiconductor chips are formed at the same places of the plurality of tape carriers and withdrawn to the same external connecting terminals through a plurality of mutually-penetrated through holes.

公开(公告)号：US06993597B2

公开(公告)日：2006-01-31

申请号：US10639445

申请日：2003-08-13

申请人： Tetsuya Nakagawa ,  Yuji Hatano ,  Yasuhiro Sagesaka ,  Toru Baji ,  Koki Noguchi

发明人： Tetsuya Nakagawa ,  Yuji Hatano ,  Yasuhiro Sagesaka ,  Toru Baji ,  Koki Noguchi

IPC分类号： G06F3/00

CPC分类号： G06F9/3885 ,  G06F1/3203 ,  G06F15/7807

摘要： A low cost, a low power consumption and a small size are three very important factors for a mobile communication terminal. A great problem is posed by the conventional technique using a DSP and a CPU independent of each other which requires two external memory systems. Also, two peripheral units are required for data input and output of the DSP and CPU. As a result, an extraneous communication overhead occurs between the DSP and the CPU. The invention realizes a mobile communication terminal system by a DSP/CPU integrated chip comprising a DSP/CPU core (500) integrated as a single bus master, an integrated external bus interface (606) and an integrated peripheral circuit interface. The memory systems and the peripheral circuits of the DSP and the CPU can thus be integrated to realize a mobile communication terminal system low in cost and power consumption and small in size.

摘要翻译： 低成本，低功耗和小尺寸是移动通信终端的三个非常重要的因素。 使用DSP和独立于彼此的CPU的传统技术提出了一个很大的问题，需要两个外部存储器系统。 此外，DSP和CPU的数据输入和输出需要两个外设单元。 因此，DSP和CPU之间会发生无关的通信开销。 本发明通过DSP / CPU集成芯片实现移动通信终端系统，其包括集成为单总线主机的DSP / CPU核心（500），集成外部总线接口（606）和集成外围电路接口。 因此，DSP和CPU的存储器系统和外围电路可以被集成以实现低成本和功耗以及体积小的移动通信终端系统。

公开(公告)号：US06611012B2

公开(公告)日：2003-08-26

申请号：US10050950

申请日：2002-01-22

申请人： Toshio Miyamoto ,  Asao Nishimura ,  Koki Noguchi ,  Satoshi Michishita ,  Masashi Horiguchi ,  Masaharu Kubo ,  Kazuyoshi Shiba

发明人： Toshio Miyamoto ,  Asao Nishimura ,  Koki Noguchi ,  Satoshi Michishita ,  Masashi Horiguchi ,  Masaharu Kubo ,  Kazuyoshi Shiba

IPC分类号： H01L25065

CPC分类号： H01L24/50 ,  H01L23/49572 ,  H01L23/49816 ,  H01L24/06 ,  H01L24/45 ,  H01L24/48 ,  H01L25/0657 ,  H01L25/105 ,  H01L27/10897 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/06136 ,  H01L2224/16245 ,  H01L2224/451 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2225/1029 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2225/107 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01021 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01055 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/12033 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15311 ,  H01L2924/15312 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/3011 ,  H01L2924/3511 ,  H01L2924/00015 ,  H01L2224/05599 ,  H01L2924/00 ,  H01L2924/00012

摘要： Described herein is a stacked package according to the present invention, wherein a plurality of tape carriers which seal semiconductor chips, are multilayered in upward and downward directions. In the stacked package, one ends of leads formed over the whole surfaces of each tape carrier are electrically connected to their corresponding connecting terminals of the semiconductor chip. Other ends of the leads are electrically connected to their corresponding through holes defined in the tape carrier. Connecting terminals common to the plurality of semiconductor chips are formed at the same places of the plurality of tape carriers and withdrawn to the same external connecting terminals through a plurality of mutually-penetrated through holes.

公开(公告)号：US06539444B1

公开(公告)日：2003-03-25

申请号：US09389227

申请日：1999-09-03

申请人： Nobukazu Kondo ,  Ikuya Kawasaki ,  Koki Noguchi

发明人： Nobukazu Kondo ,  Ikuya Kawasaki ,  Koki Noguchi

IPC分类号： G06F1300

CPC分类号： G06F13/4059 ,  Y02D10/14 ,  Y02D10/151

摘要： An information processing apparatus includes a master module serving as a transfer source, a slave module serving as a transfer destination, a bus of a source clock synchronous system, and a means for transferring a signal based upon a protocol of an acknowledge type from the slave module to the master module via the bus of the source clock synchronous system. In the information processor, the signals of the acknowledge type are also transferred in the source clock synchronous system by using a source clock signal dedicated to signals of the acknowledge type. Therefore, it is prevented that the master side fails in acquiring signals of the acknowledge type from the slave side, and the reliability of the source clock synchronous bus and the data efficiency can be improved.

摘要翻译： 信息处理装置包括：作为传送源的主模块，用作传送目的地的从模块，源时钟同步系统的总线，以及用于基于来自从设备的确认类型的协议传送信号的装置 通过源时钟同步系统的总线模块到主模块。 在信息处理器中，确认类型的信号也通过使用专用于确认类型的信号的源时钟信号在源时钟同步系统中传送。 因此，防止主机侧从从机侧获取确认类型的信号失败，并且可以提高源时钟同步总线的可靠性和数据效率。