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公开(公告)号：US20220038112A1
公开(公告)日：2022-02-03
申请号：US17322862
申请日：2021-05-17
发明人： Scott David Kee , Setu Mohta
IPC分类号： H03M1/12
摘要： Analog-to-digital converters (ADCs) with a high sampling rate and larger spurious-free dynamic range (SFDR) in the spectral domain are used in many applications, including, but not limited to, range finders, meteorology, spectroscopy, and/or coherent medical imaging. Circuit techniques for time-interleaving a set of low-sampling-rate sub-ADCs into a higher sampling-rate ADC with a larger SFDR than existing approaches are described. In one embodiment, the circuit techniques add a small number of additional units or sub-ADCs. This change in architecture enables a dynamic-selection procedure to time-interleave the set of sub-ADCs in such a way that mismatch-related non-idealities of the constituent sub-ADCs are spread in the frequency domain into a noise-like spectral shape in order to prevent the creation of spurious tones, which would otherwise deleteriously impact the SFDR.
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公开(公告)号：US20210326489A1
公开(公告)日：2021-10-21
申请号：US17315271
申请日：2021-05-08
发明人： Scott David Kee
IPC分类号： G06F21/76
摘要： Techniques in electronic systems, such as in systems comprising a CPU die and one or more external mixed-mode (analog) chips, may provide improvements advantages in one or more of system design, performance, cost, efficiency and programmability. In one embodiment, the CPU die comprises at least one microcontroller CPU and circuitry enabling the at least one CPU to have a full and transparent connectivity to an analog chip as if they are designed as a single chip microcontroller, while the interface design between the two is extremely efficient and with limited in number of wires, yet may provide improved performance without impact to functionality or the software model.
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公开(公告)号：US20210326073A1
公开(公告)日：2021-10-21
申请号：US17315267
申请日：2021-05-08
发明人： Scott David Kee
IPC分类号： G06F3/06 , G06F12/06 , G06F12/0866
摘要： A system that includes a first die with a central processing unit (CPU) and a second die electrically coupled to the first die by die-to-die interconnects is described. During operation, the first die: provides, to the second die, a set of predefined wake-up events; provides, to the second die, a message that transitions power-management control of the first die to the second die; and transitions the first die from a first operating mode to a second operating mode that has lower power consumption than that of the first operating mode. Then, the second die: determines an occurrence of a predefined wake-up event based at least in part on the set of predefined wake-up events; and provides, to the first die, information that initiates a transition of the first die from the second operating mode to the first operating mode.
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公开(公告)号：US20220222190A1
公开(公告)日：2022-07-14
申请号：US17705298
申请日：2022-03-26
发明人： Scott David Kee
摘要： Techniques in electronic systems, such as in systems comprising a CPU die and one or more external mixed-mode (analog) chips, may provide improvements advantages in one or more of system design, performance, cost, efficiency and programmability. In one embodiment, the CPU die comprises at least one microcontroller CPU and circuitry enabling the at least one CPU to have a full and transparent connectivity to an analog chip as if they are designed as a single chip microcontroller, while the interface design between the two is extremely efficient and with limited in number of wires, yet may provide improved performance without impact to functionality or the software model.
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公开(公告)号：US20210326287A1
公开(公告)日：2021-10-21
申请号：US17225057
申请日：2021-04-07
发明人： Scott David Kee
IPC分类号： G06F13/40 , G06F13/42 , G06F13/364
摘要： Techniques in electronic systems, such as in systems comprising a CPU die and one or more external mixed-mode (analog) chips, may provide improvements advantages in one or more of system design, performance, cost, efficiency and programmability. In one embodiment, the CPU die comprises at least one microcontroller CPU and circuitry enabling the at least one CPU to have a full and transparent connectivity to an analog chip as if they are designed as a single chip microcontroller, while the interface design between the two is extremely efficient and with limited in number of wires, yet may provide improved performance without impact to functionality or the software model.
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6.发明公开公开(公告)号：US20240235550A9
公开(公告)日：2024-07-11
申请号：US18383477
申请日：2023-10-25
发明人： Mohammad Radfar , Ichiro Aoki , Scott David Kee
IPC分类号： H03K19/0175 , H03K5/1252 , H03K19/0185
CPC分类号： H03K19/017509 , H03K5/1252 , H03K19/0185 , H03K19/018514
摘要： An interface circuit may convert an input electrical signal at an input node in a first power domain having a first ground or reference voltage into an output electrical signal at an output node in a second power domain having a second ground or reference voltage. Notably, a level-shifting circuit in the interface circuit may selectively electrically couple to the input node and the output node. Then, when there is electrical coupling, the level-shifting circuit may perform level shifting between the first power domain and the second power domain. The level shifting may involve: passing, using a first filter, frequencies in the input electrical signal below a first corner frequency; passing, using a second filter in parallel with the first filter, frequencies in the input electrical signal above a second corner frequency; and combining outputs of the first filter and the second filter as the output electrical signal.
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7.发明申请公开(公告)号：US20230042591A1
公开(公告)日：2023-02-09
申请号：US17712026
申请日：2022-04-01
发明人： Mohammad Radfar , Ichiro Aoki , Scott David Kee
IPC分类号： H03K19/0175 , H03K5/1252
摘要： An interface circuit may convert an input electrical signal at an input node in a first power domain having a first ground or reference voltage into an output electrical signal at an output node in a second power domain having a second ground or reference voltage. Notably, a level-shifting circuit in the interface circuit may selectively electrically couple to the input node and the output node. Then, when there is electrical coupling, the level-shifting circuit may perform level shifting between the first power domain and the second power domain. The level shifting may involve: passing, using a first filter, frequencies in the input electrical signal below a first corner frequency; passing, using a second filter in parallel with the first filter, frequencies in the input electrical signal above a second corner frequency; and combining outputs of the first filter and the second filter as the output electrical signal.
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公开(公告)号：US20220260700A1
公开(公告)日：2022-08-18
申请号：US17556362
申请日：2021-12-20
发明人： Setu Mohta , Scott David Kee , Aravind Loke
摘要： An integrated circuit that includes an analog frequency-selective gain filter having a frequency-selective gain corresponding to a high-pass filter prior to an analog-to-digital converter (ADC) is described. During operation, the analog frequency-selective gain filter may provide frequency-selective gain (such as a high-pass filter characteristic) to an electrical signal corresponding to a received signal (such as a LiDAR signal, a sonar signal, an ultrasound signal and/or a radar signal) in a ranging receiver. Note that the received signal may correspond to a received frequency-modulated continuous-wave (FMCW) signal. Moreover, the integrated circuit may include a digital processing circuit after the ADC and control logic that instructs the digital processing circuit to characterize the frequency-selective gain (such as an amplitude and/or a phase at a frequency) during a calibration mode. Furthermore, the digital processing circuit may correct an output signal from the ADC based at least in part on the characterized frequency-selective gain.
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公开(公告)号：US20240126708A1
公开(公告)日：2024-04-18
申请号：US18536264
申请日：2023-12-12
发明人： Scott David Kee
IPC分类号： G06F13/26 , G06F3/06 , G06F12/06 , G06F12/0866 , G06F13/14 , G06F13/16 , G06F13/28 , G06F13/364 , G06F13/40 , G06F13/42 , G06F21/76
CPC分类号： G06F13/26 , G06F3/0659 , G06F3/0679 , G06F12/0638 , G06F12/0866 , G06F13/14 , G06F13/1668 , G06F13/1684 , G06F13/28 , G06F13/364 , G06F13/4027 , G06F13/4068 , G06F13/4282 , G06F21/76 , G06F2213/0062 , G06F2213/40 , G06F2221/2103
摘要： Techniques in electronic systems, such as in systems comprising a CPU die and one or more external mixed-mode (analog) chips, may provide improvements advantages in one or more of system design, performance, cost, efficiency and programmability. In one embodiment, the CPU die comprises at least one microcontroller CPU and circuitry enabling the at least one CPU to have a full and transparent connectivity to an analog chip as if they are designed as a single chip microcontroller, while the interface design between the two is extremely efficient and with limited in number of wires, yet may provide improved performance without impact to functionality or the software model.
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公开(公告)号：US20230185744A1
公开(公告)日：2023-06-15
申请号：US17943183
申请日：2022-09-12
发明人： Scott David Kee
IPC分类号： G06F13/26 , G06F13/40 , G06F3/06 , G06F12/06 , G06F12/0866 , G06F13/16 , G06F13/28 , G06F13/364 , G06F13/42 , G06F13/14 , G06F21/76
CPC分类号： G06F13/26 , G06F13/4027 , G06F3/0659 , G06F3/0679 , G06F12/0638 , G06F12/0866 , G06F13/1668 , G06F13/28 , G06F13/364 , G06F13/4068 , G06F13/4282 , G06F13/14 , G06F21/76 , G06F13/1684 , G06F2213/0062 , G06F2213/40 , G06F2221/2103
摘要： Techniques in electronic systems, such as in systems comprising a CPU die and one or more external mixed-mode (analog) chips, may provide improvements advantages in one or more of system design, performance, cost, efficiency and programmability. In one embodiment, the CPU die comprises at least one microcontroller CPU and circuitry enabling the at least one CPU to have a full and transparent connectivity to an analog chip as if they are designed as a single chip microcontroller, while the interface design between the two is extremely efficient and with limited in number of wires, yet may provide improved performance without impact to functionality or the software model.
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