公开(公告)号：US11688347B2

公开(公告)日：2023-06-27

申请号：US17620398

申请日：2020-11-03

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Li Xiao ,  Haoliang Zheng ,  Hao Chen ,  Minghua Xuan ,  Dongni Liu ,  Seungwoo Han ,  Liang Chen ,  Jiao Zhao ,  Xue Dong

IPC: G09G3/3258 ,  G09G3/3291

CPC classification number: G09G3/3258 ,  G09G3/3291

Abstract: A pixel circuit includes a driving circuit, a first control circuit and a second control circuit. The driving circuit is configured to receive a data signal in response to a scan signal, and generate, in response to a first enable signal, a driving signal according to a first voltage and the data signal. The first control circuit is configured to: receive a first input signal in response to a first control signal, and transmit a third input signal in response to the first input signal; and receive a second input signal in response to a second control signal, and transmit a second enable signal in response to the second input signal. The second control circuit is configured to transmit the driving signal to an element to be driven in response to one of the third input signal and the second enable signal.

公开(公告)号：US11508294B2

公开(公告)日：2022-11-22

申请号：US17530101

申请日：2021-11-18

Applicant: BOE Technology Group Co., Ltd.

Inventor： Jiao Zhao ,  Seungwoo Han ,  Haoliang Zheng ,  Minghua Xuan ,  Li Xiao ,  Dongni Liu ,  Liang Chen ,  Hao Chen

IPC: G09G3/32

Abstract: The present application provides a pixel circuit, a pixel driving method and a display device. The pixel circuit is to be coupled to a to-be-driven element. The pixel circuit includes a first energy storage circuit, a driving circuit, a light-emitting control circuit, a data writing circuit, and a compensation control circuit. The compensation control circuit is configured to, under control of a third control signal, control conduction between the first node and the first terminal of the driving circuit, and control conduction between the second node and the second terminal of the driving circuit.

公开(公告)号：US11282424B2

公开(公告)日：2022-03-22

申请号：US16301843

申请日：2018-04-19

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Guangliang Shang ,  Seungwoo Han

IPC: G09G3/20 ,  G01B7/16 ,  G09G3/00 ,  G06F3/03

Abstract: The present disclosure is related to a flexible display panel. The flexible display panel may include a display substrate, a plurality of pixel units arranged in an array on the display substrate, and at least a strain sensor on the display substrate. The strain sensor may be arranged corresponding to a region comprising at least one of the plurality of pixel units. The strain sensor may be configured to detect deformation in the region comprising at least one of the plurality of pixel units and to generate a detection signal.

公开(公告)号：US10755665B2

公开(公告)日：2020-08-25

申请号：US16450226

申请日：2019-06-24

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Seungwoo Han ,  Guangliang Shang

IPC: G09G3/36 ,  G02F1/1362 ,  G02F1/1368

Abstract: A pixel circuit, an array substrate, a display panel and an electronic apparatus are provided. The pixel circuit includes: a data writing sub-circuit, a first data storage sub-circuit, a second data storage sub-circuit and a light-emitting control sub-circuit. The data writing sub-circuit writes, under the control of a signal input from a first control signal input end, to the first data storage sub-circuit a data signal input from a data signal input end, and writes, under the control of a signal input from a second control signal input end, to the second data storage sub-circuit the data signal input from the data signal input end. The light-emitting control sub-circuit controls on/off states of corresponding thin film transistors in accordance with data signals output from the first data storage sub-circuit and the second data storage sub-circuit, so that different gray-scales may be rendered.

公开(公告)号：US20180108426A1

公开(公告)日：2018-04-19

申请号：US15504119

申请日：2016-08-12

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Haoliang Zheng ,  Seungwoo Han ,  Xing Yao ,  Hyunsic Choi ,  Guangliang Shang ,  Mingfu Han ,  Yunsik Im ,  Jungmok JUN ,  Xue Dong

IPC: G11C19/28 ,  G09G3/36 ,  H01L27/12 ,  G11C19/18

CPC classification number: G11C19/28 ,  G09G3/20 ,  G09G3/3677 ,  G09G3/3688 ,  G09G2310/0267 ,  G09G2310/0286 ,  G11C19/184 ,  H01L27/1222 ,  H01L27/124 ,  H01L27/1251

Abstract: The present application discloses a method of driving a gate driving circuit in an operation cycle divided into a first sub-cycle and a second sub-cycle, including providing a gate driving circuit having a first plurality of shift register units with a second plurality of shift register units, the first plurality of shift register units being configured so that each odd/even numbered shift register unit includes a first bias-control terminal to receive a first/second bias signal CLK1/CLK2, a second bias-control terminal to receive a second/first bias signal CLK2/CLK1, and a first control level terminal provided with a first control voltage VC1, the second plurality of shift register units being configured so that each odd/even numbered shift register unit includes a third bias-control terminal to receive a third/fourth bias signal CLK3/CLK4, a fourth bias-control terminal to receive a fourth/third bias signal CLK4/CLK3, and a second control level terminal provided with a second control voltage VC2; configuring the first bias signal CLK1 and the second bias signal CLK2 as first pair of clock signals at respective turn-on level and turn-off level with inverted phase in the first sub-cycle; setting the first control voltage VC1 to a turn-off level so that the first plurality of shift register units is controlled along with the first pair of clock signals to respectively output corresponding gate driving output signals in an output phase within the first sub-cycle; setting both the third bias signal CLK3 and the fourth bias signal CLK4 to a turn-off level and the second control voltage VC2 to turn-on level during the first sub-cycle; configuring the third bias signal CLK3 and the fourth bias signal CLK4 as second pair of clock signals at respective turn-on level and turn-off level with inverted phase in the second sub-cycle; setting the second control voltage VC2 to a turn-off level so that the second plurality of shift register units are controlled along with the second pair of clock signals to respectively output corresponding gate driving output signals in an output phase within the second sub-cycle; and setting the first bias signal CLK1 and the second bias signal CLK2 to a turn-off level and the second control voltage VC1 to a turn-on level during the second sub-cycle.

公开(公告)号：US20170270851A1

公开(公告)日：2017-09-21

申请号：US15503051

申请日：2016-08-04

Applicant: Boe Technology Group Co., Ltd.

Inventor： Guangliang Shang ,  Seungwoo Han ,  Zhihe Jin ,  Mingfu Han ,  Xing Yao ,  Haoling Zheng ,  Yunsil IM ,  Seungmin Lee ,  Haijun Qiu ,  Jungmok Jun ,  Xue Dong

IPC: G09G3/20

CPC classification number: G09G3/2092 ,  G09G3/3266 ,  G09G3/3677 ,  G09G2310/0286 ,  G09G2310/0289 ,  G09G2310/08 ,  G11C19/28

Abstract: A shift register is disclosed including an input module, an output module, a first reset module, a first pull-down module and a second pull-down module. The first pull-down module is configured to supply a reference signal to a first node and an output terminal in response to an active level of a first control signal. The second pull-down module is configured to supply the reference signal to the first node and the output terminal in response to an active level of a second control signal. The active levels of the first control signal and the second control signal occur alternately. Also disclosed are a gate driver circuit and a display apparatus.

公开(公告)号：US09437145B2

公开(公告)日：2016-09-06

申请号：US14497385

申请日：2014-09-26

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Seungwoo Han ,  Yuanbo Zhang ,  Guangliang Shang

IPC: G09G3/36

CPC classification number: G09G3/3607 ,  G09G3/3696 ,  G09G2300/0408 ,  G09G2310/027 ,  G09G2320/0233 ,  G09G2320/0276 ,  G09G2320/0673 ,  G09G2330/06

Abstract: The present disclosure provides a gamma reference voltage generating circuit including a center voltage generation unit, a gamma reference voltage generation unit configured to generate positive and negative gamma reference voltages and control the positive gamma reference voltage and the negative gamma reference voltage to be symmetrical with respect to the center voltage; a first voltage divider unit including a first terminal for receiving the positive gamma reference voltage and a second terminal for receiving the center voltage; and a second voltage divider unit including a first terminal coupled with the second terminal of the first voltage divider unit and a second terminal for receiving the negative gamma reference voltage.

Abstract translation: 本公开提供了一种伽马参考电压产生电路，其包括中心电压产生单元，伽马参考电压产生单元，被配置为产生正和负伽马参考电压，并且控制正伽马参考电压和负伽马参考电压相对于对称 到中心电压; 第一分压器单元，包括用于接收正伽马参考电压的第一端子和用于接收中心电压的第二端子; 以及第二分压器单元，包括与第一分压器单元的第二端子耦合的第一端子和用于接收负的伽马参考电压的第二端子。

公开(公告)号：US20160064098A1

公开(公告)日：2016-03-03

申请号：US14416029

申请日：2014-05-21

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Seungwoo Han ,  Xing Yao

IPC: G11C19/28 ,  G09G3/32

CPC classification number: G11C19/28 ,  G09G3/3225 ,  G09G3/3266 ,  G09G2300/0842 ,  G09G2310/0286

Abstract: According to an embodiment of the present disclosure, a shift register unit may include: a first control module, configured to transmit a start signal to a first node; a second control module, configured to pull a potential of a second node to a potential different from a potential of the first node, under a control of a first clock signal; a carry output module, configured to output a carry signal according to the potential of the first node and the potential of the second node; and a shift output module, configured to output a shift signal according to the potential of the first node and the potential of the second node.

Abstract translation: 根据本公开的实施例，移位寄存器单元可以包括：第一控制模块，被配置为将起始信号发送到第一节点; 第二控制模块，被配置为在第一时钟信号的控制下将第二节点的电位拉到与所述第一节点的电位不同的电位; 进位输出模块，被配置为根据第一节点的电位和第二节点的电位输出进位信号; 以及移位输出模块，被配置为根据第一节点的电位和第二节点的电位来输出移位信号。

公开(公告)号：US11176886B2

公开(公告)日：2021-11-16

申请号：US16319185

申请日：2018-05-14

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Lijun Yuan ,  Mingfu Han ,  Zhichong Wang ,  Haoliang Zheng ,  Seungwoo Han ,  Guangliang Shang

IPC: G09G3/3258 ,  G09G3/3266 ,  G09G3/3275 ,  G09G3/3233 ,  G09G3/3208 ,  G09G3/3225

Abstract: The present disclosure discloses a circuit, a driving method thereof, a display panel and a display device. The circuit may include: a signal control module, a compensation control module, an initialization module, a data writing module, a driving control module, and a light emitting device. With the signal control module which is cooperated with other modules, the threshold voltage compensation time of the driving transistor can be increased, and the threshold voltage compensation can be ensured, thereby improving the image display quality.

公开(公告)号：US20210335314A1

公开(公告)日：2021-10-28

申请号：US16332902

申请日：2018-09-26

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Lijun Yuan ,  Seungwoo Han ,  Guangliang Shang

IPC: G09G3/36

Abstract: The present disclosure relates to a pixel circuit. The pixel circuit may include a switch sub-circuit (10), a storage sub-circuit (20), and a driving sub-circuit (30). The storage sub-circuit (20) may include a first storage transistor (Tf1) and a second storage transistor (Tf2). Both the first storage transistor (Tf1) and the second storage transistor (Tf2) may be floating gate transistors. The storage sub-circuit (20) and the driving sub-circuit (30) may be configured to transmit a data signal from one of a plurality of data lines to a pixel electrode under control of the switch sub-circuit (10).