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公开(公告)号：US20240215342A1
公开(公告)日：2024-06-27
申请号：US17915522
申请日：2021-05-28
Inventor： Yongchao HUANG , Jingang FANG , Jun CHENG , Xinxin WANG , Jun LIU , Qinghe WANG , Leilei CHENG , Bin ZHOU , Ce ZHAO , Liangchen YAN
IPC: H10K59/126 , H10K59/12 , H10K59/122
CPC classification number: H10K59/126 , H10K59/1201 , H10K59/122
Abstract: A display panel includes a substrate, a driving layer and a light-emitting control layer. The driving layer is provided with a plurality of driving transistors arranged into a plurality of transistor rows in a column direction. The light-emitting control layer includes a plurality of light-emitting devices arranged into a plurality of device rows in the column direction, the device rows is spaced apart by the transistor row in the column direction, and the transistor rows is spaced apart by the device row in the column direction. The pixel-defining layer is provided with a plurality of blocking grooves recessed toward the substrate, the plurality of blocking grooves are arranged in the column direction, at least one of the plurality of blocking grooves is arranged between the transistor row and the device row adjacent in the column direction, and a light-shielding layer is arranged in the blocking groove.
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公开(公告)号：US20230200128A1
公开(公告)日：2023-06-22
申请号：US17615835
申请日：2021-02-26
Inventor： Tongshang SU , Bin ZHOU , Jun CHENG , Qinghe WANG , Yongchao HUANG , Dacheng ZHANG , Liangchen YAN
IPC: H10K59/121 , H10K59/35 , H10K59/12 , H10K71/00 , H10K59/122
CPC classification number: H10K59/1213 , H10K59/353 , H10K59/1201 , H10K71/00 , H10K59/122
Abstract: The present disclosure provides a display substrate, a method for manufacturing the same, and a display device. The display substrate includes a drive circuit layer disposed on a base substrate and a light emitting structure layer disposed on a side of the drive circuit layer away from the base substrate. The light emitting structure layer includes an anode, an organic light emitting layer, a cathode, and an auxiliary electrode. The organic light emitting layer is respectively connected to the anode and the cathode, and the cathode is connected to the auxiliary electrode; in a plane parallel to the display substrate, an edge of the auxiliary electrode is provided with a structure depressed towards a center of the auxiliary electrode.
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公开(公告)号：US20220392987A1
公开(公告)日：2022-12-08
申请号：US17770045
申请日：2021-07-20
Inventor： Ning LIU , Dacheng ZHANG , Jun GENG , Feng ZHANG , Yang PAN , Bin ZHOU , Liangchen YAN
Abstract: A display substrate, a preparation method therefor, and a display apparatus. The display substrate includes a first metal layer, a metal oxide layer and a second metal layer, which are stacked on a base. The metal oxide layer includes a first active layer, the first active layer including a channel region, a source transition region, and a drain transition region, wherein both the source transition region and the drain transition region comprise a first region and a second region.
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公开(公告)号：US20210367017A1
公开(公告)日：2021-11-25
申请号：US17241703
申请日：2021-04-27
Inventor： Ning LIU , Jun LIU , Wei SONG , Qinghe WANG , Bin ZHOU , Liangchen YAN
IPC: H01L27/32
Abstract: An array substrate, a method for manufacturing the array substrate and a display device are provided. The array substrate includes: a base substrate, and a thin film transistor, a storage capacitor, and a lapping pattern for connecting the thin film transistor to the storage capacitor arranged on the base substrate; wherein the thin film transistor includes a semiconductor layer, a gate insulation layer, a gate electrode, an interlayer insulation layer, a source electrode and a drain electrode arranged sequentially in that order; the interlayer insulation layer includes at least two inorganic insulation layers and at least one organic insulation layer laminated one on another, and both a layer proximate to the base substrate and a layer distal to the base substrate in the interlayer insulation layer are the inorganic insulation layers.
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公开(公告)号：US20200035716A1
公开(公告)日：2020-01-30
申请号：US16396726
申请日：2019-04-28
Applicant: BOE TECHNOLOGY GROUP CO., LTD.
Inventor： Bin ZHOU , Binbin CAO , Liangchen YAN , Dongfang WANG , Ce ZHAO , Luke DING , Jun LIU
IPC: H01L27/12
Abstract: The present disclosure is in the field of display technologies, and provides an array substrate including an IGZO film layer, a gate layer, and a gate insulating layer. The gate layer is provided with broken lines at a position thereof overlapping the IGZO film layer to form a first gate line and a second gate line. The gate insulating layer is disposed between the IGZO film layer and the gate layer, and is provided with at least two through holes thereon, in which the first gate line is connected with the IGZO film layer through one of the through holes, and the second gate line is connected with the IGZO film layer through another through hole, thus, connecting the IGZO film layer in series into the gate layer.
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Patent Agency Ranking
公开(公告)号：US20180315777A1
公开(公告)日：2018-11-01
申请号：US15508484
申请日：2016-05-20
Inventor： Liangchen YAN , Guangcai YUAN , Xiaoguang XU , Lei WANG , Junbiao PENG , Linfeng LAN
IPC: H01L27/12 , H01L29/423 , H01L29/417 , H01L29/786 , H01L29/66
CPC classification number: H01L29/7869 , H01L29/66969
Abstract: A thin-film transistor (TFT) is provided in this disclosure, which comprises Sn-doped ZrO2. This oxide semiconductor material can be used in a semiconductor layer of a TFT, and a mass percentage of Sn doped in the ZrO2 is about 1%-95%. A semiconductor layer comprising Sn-doped ZrO2 exhibits higher acid tolerance after annealing. This disclosure also provides a method for fabricating a TFT, which comprises: (i) forming a semiconductor layer, wherein the semiconductor layer comprises Sn-doped ZrO2, and (ii) annealing the semiconductor layer.
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7.发明申请OXIDE SEMICONDUCTOR THIN FILM, THIN FILM TRANSISTOR, MANUFACTURING METHOD AND DEVICE 有权氧化物半导体薄膜，薄膜晶体管，制造方法和器件公开(公告)号：US20170077307A1
公开(公告)日：2017-03-16
申请号：US15123177
申请日：2015-09-02
Inventor： Guangcai YUAN , Liangchen YAN , Xiaoguang XU , Lei WANG , Junbiao PENG , Linfeng LAN
IPC: H01L29/786 , H01L27/12 , H01L29/24
CPC classification number: H01L29/7869 , H01L21/02 , H01L21/02189 , H01L21/02194 , H01L21/02565 , H01L21/34 , H01L27/1225 , H01L29/24 , H01L29/66969 , H01L29/78696
Abstract: This disclosure discloses an oxide semiconductor thin film, a thin film transistor, a manufacturing method and a device, belonging to the field of flat panel display. The oxide semiconductor thin film is made of an oxide containing zirconium and indium. A method of manufacturing the oxide semiconductor thin film comprises preparing a target using the oxide containing zirconium and indium, and sputtering the target to obtain the oxide semiconductor thin film.
Abstract translation: 本公开公开了属于平板显示器领域的氧化物半导体薄膜，薄膜晶体管，制造方法和装置。 氧化物半导体薄膜由含有锆和铟的氧化物制成。 制造氧化物半导体薄膜的方法包括使用含有锆和铟的氧化物制备靶，溅射靶以获得氧化物半导体薄膜。
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公开(公告)号：US20240395852A1
公开(公告)日：2024-11-28
申请号：US18262456
申请日：2022-09-29
Inventor： Leilei CHENG , Cheng XU , Jie LIU , Bin ZHOU , Liangchen YAN , Haitao WANG , Ao SHENG
Abstract: Embodiments of the present disclosure provide an array substrate and a related display panel and a method of manufacturing thereof. An array substrate comprises: a substrate; a first light-shielding layer; a first dielectric layer which comprises a first opening; a transistor, which comprises an active layer with a first source/drain region, a second source/drain region, and a channel region; a second dielectric layer, which comprises a second opening, wherein a second projection of the second opening on the substrate at least partially overlaps with a first projection of the first opening on the substrate; a first conductive layer; a third dielectric layer, which comprises a third opening, wherein a third projection of the third dielectric layer on the substrate at least partially overlaps with the first projection and the second projection; a fourth dielectric layer, which comprises a fourth opening, wherein a fourth projection of the fourth dielectric layer on the substrate at least partially overlaps with the first projection of the first opening, the second projection of the second opening, and the third projection of the third opening; and a second conductive layer.
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公开(公告)号：US20240276778A1
公开(公告)日：2024-08-15
申请号：US18023730
申请日：2022-04-26
Inventor： Ning LIU , Yang ZHANG , Haitao WANG , Zhengchao ZHANG , Bin ZHOU , Liangchen YAN
IPC: H10K59/122 , H10K59/12 , H10K59/131 , H10K59/80 , H10K102/00
CPC classification number: H10K59/122 , H10K59/1201 , H10K59/131 , H10K59/80522 , H10K2102/351
Abstract: The present disclosure provides a display substrate and a preparation method thereof, and a display apparatus. The display substrate comprises a display region and a transparent region, and on a plane perpendicular to the display substrate, the display substrate at least comprises a drive structure layer and a light-emitting structure layer which are arranged on a substrate, wherein the drive structure layer at least comprises an inorganic insulation layer, and the light-emitting structure layer at least comprises a pixel definition layer; the drive structure layer of the display region further comprises a planarization layer arranged on the inorganic insulation layer, and a pixel definition layer is arranged on the planarization layer and is in contact with the planarization layer; and at least one groove is provided on the inorganic insulation layer of the transparent region, and the pixel definition layer fills the groove located in the transparent region.
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公开(公告)号：US20210296365A1
公开(公告)日：2021-09-23
申请号：US17206254
申请日：2021-03-19
Inventor： Jun LIU , Liangchen YAN , Bin ZHOU , Yang ZHANG , Tongshang SU , Wei LI , Liusong NI
IPC: H01L27/12
Abstract: A display substrate, a method for forming the display substrate and a display device are provided. The display substrate includes: a first conductive pattern located on a base substrate, where a ring-shaped conductive protection structure is arranged at an edge of a preset region of the first conductive pattern and surrounds the preset region, and the conductive protection structure is made of an anti-dry-etching material; an insulation layer covering the first conductive pattern; and a second conductive pattern located on a side of the insulation layer away from the first conductive pattern, where the second conductive pattern is electrically connected to the first conductive pattern through the via-hole.
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