Abstract:
An image processing method includes: acquiring first image data of a first image, the first image data including pixel values of a plurality of pixels in the first image; a first compression-allowed region existing in the first image, obtaining region expression information of the first compression-allowed region, the first compression-allowed region including a region where a plurality of first pixels are located, and a difference between pixel values of any two first pixels in the plurality of first pixels being within a preset range; determining a region pixel value of the first compression-allowed region according to a pixel value of at least one first pixel in the first compression-allowed region; and generating second image data of the first image, the second image data including region expression information and the region pixel value of the first compression-allowed region.
Abstract:
A display panel includes a liquid crystal cell, a light guide plate, and at least one light source. The light guide plate is attached to a surface of the liquid crystal cell in a thickness direction of the liquid crystal. The light guide plate includes a first surface, a second surface and side surfaces. In a thickness direction of the light guide plate, the first surface is opposite to the second surface, and the side faces are located between the first surface and the second surface. The first surface is closer to the liquid crystal cell than the second surface. A light source is disposed on at least a partial region in at least one side face. The light guide plate is configured such that light incident on the second surface in light from the light source is totally reflected, and then exits from the first surface.
Abstract:
The present disclosure provides a chip structure, a packaging structure and a manufacturing method for the chip structure. The chip structure includes at least one chip body, each of which includes at least one radio frequency front-end device; the chip structure further includes a redistribution layer stacked on the chip body and at least one pin on the redistribution layer; each radio frequency front-end device corresponds to one pin, which is electrically connected to the radio frequency front-end device through an electrical connector extending through the redistribution layer; an extending direction of the radio frequency front-end device is consistent with an extending direction of the pin corresponding to the radio frequency front-end device; a surface of the pin distal to the redistribution layer is a first plane. In the present disclosure, with the first plane, the chip may be directly and electrically connected to a flexible circuit board.
Abstract:
A detection substrate and a ray detector are disclosed. The detection substrate includes a base substrate; a plurality of detection pixel circuits, located on the base substrate; a first passivation layer, located on the side, facing away from the base substrate, of the detection pixel circuits; a planarization layer, located on the side, facing away from the base substrate, of the first passivation layer, where the surface of the side, facing away from the first passivation layer, of the planarization layer is a plane; and a plurality of photosensitive devices; where the photosensitive devices are electrically connected to the detection pixel circuits in a one-to-one correspondence through vias penetrating through the first passivation layer and the planarization layer, and each photosensitive device includes a first portion and a second portion.
Abstract:
The present disclosure provides a flat panel detection substrate, a fabricating method thereof and a flat panel detector. The flat panel detection substrate according to the present disclosure includes a base substrate; a bias electrode and a sense electrode on the base substrate; and a semiconductor layer over the bias electrode and the sense electrode, the semiconductor layer having a thickness greater than 100 nm.
Abstract:
The present disclosure relates to the OLED display technology. There are provided a pixel circuit, a driving circuit, an array substrate and a display device, which are supplied with the voltage by the light emitting operation voltage when the pixel circuit enters the light emitting stage, by inputting an inverse signal synchronized with the pre-charging control voltage at the input terminal of the light emitting operation voltage to ensure a stable output of the current by the circuit at the light emitting stage. Also, it does not require an arrangement of an external voltage input terminal which will affect the aperture ratio, thereby increasing the aperture ratio of the OLED employing the current-driven pixel circuit while ensuring the stable output of the current by the current-driven circuit, and thus increasing the lifetime of the OLED employing the current-driven pixel circuit.
Abstract:
The gate driver circuit is connected to a row of pixel units, each pixel unit includes a pixel driving module and a light-emitting device connected to each other, the pixel driving module including a driving transistor, a driving module and a compensating module, the compensating module being connected to a gate scanning signal, and the driving module being connected to a driving control signal and a driving voltage. The gate driver circuit includes a row pixel controlling unit configured to provide the gate scanning signal to the compensating module and provide the driving voltage to the driving module, so as to control the compensating module to compensate for a threshold voltage of the driving transistor; and a driving control unit configured to provide the driving control signal to the driving module so as to control the driving module to drive the light-emitting device.
Abstract:
The gate driver circuit is connected to a row of pixel unit, each includes a pixel driving module and a light-emitting device connected to each other, the pixel driving module including a driving transistor, a driving module and a compensating module, the compensating module is connected to a first row scanning signal, and the driving module is connected to a second row scanning signal and a driving voltage. The gate driver circuit further includes a row pixel controlling unit configured to provide the first row scanning signal to the compensating module and provide the second row scanning signal and the driving voltage to the driving module, so as to control the compensating module to compensate for a threshold voltage of the driving transistor and control the driving module to drive the light-emitting device.
Abstract:
The disclosure provides a video image transmission method, including: capturing and uploading video images to a cloud server in real time, by a video image capture terminal; acquiring first speed information of uploading the video images by the video image capture terminal and second speed information of receiving the video images by the cloud server; determining, according to first speed information, second speed information and a current ratio n of a first frame rate at which the video image capture terminal captures the video images and a second frame rate at which the video image capture terminal uploads the video images, a target ratio m of the first frame rate to the second frame rate, the target ratio m and the current ratio n being both positive integers; and adjusting, according to the target ratio m, a speed at which the video image capture terminal uploads the video images, to match an adjusted speed at which the video image capture terminal uploads the video images with a speed at which the cloud server receives the video images.
Abstract:
Embodiments of the present disclosure provide a pixel circuit and a drive method thereof, and a detector including the pixel circuit. The pixel circuit includes a photoelectric conversion circuit, a reset circuit, an amplifying circuit, a first control circuit, a second control circuit, a storage circuit, and an output circuit. The photoelectric conversion circuit is configured to convert an optical signal into an electric signal. The reset circuit is configured to reset a voltage of the first node. The amplifying circuit is configured to amplify the voltage of the first node. The first control circuit is configured to control a voltage of the second node. The second control circuit is configured to control a voltage of the third node. The storage circuit is configured to store an electric charge corresponding to the voltage outputted from the amplifying circuit. The output circuit is configured to output the stored electric charge.