公开(公告)号：US09344268B1

公开(公告)日：2016-05-17

申请号：US14668165

申请日：2015-03-25

Applicant: Broadcom Corporation

Inventor： Ali Nazemi ,  Burak Catli ,  Wayne Wah-Yuen Wong ,  Kangmin Hu ,  Hyo Gyuem Rhew ,  Delong Cui ,  Jun Cao ,  Bo Zhang ,  Afshin Doctor Momtaz

IPC: H04L7/00 ,  H04L7/033

CPC classification number: H04J3/0685 ,  H04J3/047 ,  H04L7/0025

Abstract: A phase alignment architecture enhances the performance of communication systems. The architecture aligns a divided clock (e.g., in differential Inphase (I) and Quadrature (Q)) to a main clock, even at extremely high speeds, where skew variations of the divided clock are comparable to the main clock period. The improvement in phase alignment facilitates ultra high-speed communications.

Abstract translation: 相位对准架构增强了通信系统的性能。 即使在非常高的速度下，分频时钟的分频时钟（例如，差分同相（I）和正交（Q））与主时钟对准，其中分频时钟的偏移变化与主时钟周期相当。 相位对准的改进有助于超高速通信。

公开(公告)号：US20140146922A1

公开(公告)日：2014-05-29

申请号：US13720623

申请日：2012-12-19

Applicant: BROADCOM CORPORATION

Inventor： Ali Nazemi ,  Mahmoud Reza Ahmadi ,  Tamer Ali ,  Bo Zhang ,  Mohammed Abdul-Latif ,  Namik Kocaman ,  Afshin Momtaz

IPC: H04L25/02

CPC classification number: H04L7/00 ,  H04L7/002 ,  H04L25/0272 ,  H04L25/0292 ,  H04L25/0296 ,  H04L25/06

Abstract: Techniques are described herein that provide an interface for receiving and deserializing digital bit stream(s). For instance, a receiver for a high-speed deserializer may include digital slicers, a digital phase interpolator, and a digital clock phase generator. The digital slicers may be configured to determine a digital value of a data input. The digital phase interpolator may be configured to generate an interpolated clock signal based on input clock signals that correspond to respective phases of a reference clock. The phase of the interpolated clock tracks the data input to the receiver through a clock recovery loop. The digital clock phase generator may be configured to generate output clock signals to control timing of the respective digital slicers. The receiver may further include a single digital eye monitor configured to monitor a data eye of the data input.

Abstract translation: 这里描述了提供用于接收和反序列化数字比特流的接口的技术。 例如，用于高速解串器的接收器可以包括数字限幅器，数字相位内插器和数字时钟相位发生器。 数字限幅器可以被配置为确定数据输入的数字值。 数字相位插值器可以被配置为基于对应于参考时钟的各个相位的输入时钟信号来产生内插时钟信号。 内插时钟的相位通过时钟恢复循环跟踪输入到接收器的数据。 数字时钟相位发生器可以被配置为产生输出时钟信号以控制各个数字限幅器的定时。 接收器还可以包括被配置为监视数据输入的数据眼睛的单个数字眼睛监视器。

公开(公告)号：US08958501B2

公开(公告)日：2015-02-17

申请号：US13720623

申请日：2012-12-19

Applicant: Broadcom Corporation

Inventor： Ali Nazemi ,  Mahmoud Reza Ahmadi ,  Tamer Ali ,  Bo Zhang ,  Mohammed Abdul-Latif ,  Namik Kocaman ,  Afshin Momtaz

IPC: H03K9/00 ,  H04L7/00 ,  H04L25/02 ,  H04L25/06

CPC classification number: H04L7/00 ,  H04L7/002 ,  H04L25/0272 ,  H04L25/0292 ,  H04L25/0296 ,  H04L25/06

Abstract: Techniques are described herein that provide an interface for receiving and deserializing digital bit stream(s). For instance, a receiver for a high-speed deserializer may include digital slicers, a digital phase interpolator, and a digital clock phase generator. The digital slicers may be configured to determine a digital value of a data input. The digital phase interpolator may be configured to generate an interpolated clock signal based on input clock signals that correspond to respective phases of a reference clock. The phase of the interpolated clock tracks the data input to the receiver through a clock recovery loop. The digital clock phase generator may be configured to generate output clock signals to control timing of the respective digital slicers. The receiver may further include a single digital eye monitor configured to monitor a data eye of the data input.

Abstract translation: 这里描述了提供用于接收和反序列化数字比特流的接口的技术。 例如，用于高速解串器的接收器可以包括数字限幅器，数字相位内插器和数字时钟相位发生器。 数字限幅器可以被配置为确定数据输入的数字值。 数字相位插值器可以被配置为基于对应于参考时钟的各个相位的输入时钟信号来产生内插时钟信号。 内插时钟的相位通过时钟恢复循环跟踪输入到接收器的数据。 数字时钟相位发生器可以被配置为产生输出时钟信号以控制各个数字限幅器的定时。 接收器还可以包括被配置为监视数据输入的数据眼睛的单个数字眼睛监视器。

公开(公告)号：US20140104086A1

公开(公告)日：2014-04-17

申请号：US13754374

申请日：2013-01-30

Applicant: BROADCOM CORPORATION

Inventor： Bo Zhang ,  Ali Nazemi ,  Mahmoud Reza Ahmadi ,  Afshin Momtaz ,  Heng Zhang ,  Hassan Maarefi

IPC: H03M1/10 ,  H03M1/36

CPC classification number: H03M1/1009 ,  H03M1/069 ,  H03M1/1023 ,  H03M1/141 ,  H03M1/188 ,  H03M1/361

Abstract: Methods and apparatuses are described for a DSP receiver with an analog-to-digital converter (ADC) having high speed, low BER performance with low power and area requirements. Speed is increased for multi-path ADC configurations by resolving a conventional bottleneck. ADC performance is improved by integrating calibration and error detection and correction, such as distributed offset calibration and redundant comparators. Power and area requirements are dramatically reduced by using low BER rectification to nearly halve the number of comparators in a conventional high speed, low BER flash ADC.

Abstract translation: 描述了具有模数转换器（ADC）的DSP接收机的方法和装置，具有高速度，低BER性能，低功率和面积要求。 通过解决传统的瓶颈，提高了多路径ADC配置的速度。 通过集成校准和错误检测和校正（例如分布式偏移校准和冗余比较器）来提高ADC性能。 通过使用低BER整流将传统高速，低BER闪存ADC中的比较器数量减半，功率和面积要求大大降低。

公开(公告)号：US08836553B2

公开(公告)日：2014-09-16

申请号：US13754374

申请日：2013-01-30

Applicant: Broadcom Corporation

Inventor： Bo Zhang ,  Ali Nazemi ,  Mahmoud Reza Ahmadi ,  Afshin Momtaz ,  Heng Zhang ,  Hassan Maarefi

IPC: H03M1/10

CPC classification number: H03M1/1009 ,  H03M1/069 ,  H03M1/1023 ,  H03M1/141 ,  H03M1/188 ,  H03M1/361

Abstract: Methods and apparatuses are described for a DSP receiver with an analog-to-digital converter (ADC) having high speed, low BER performance with low power and area requirements. Speed is increased for multi-path ADC configurations by resolving a conventional bottleneck. ADC performance is improved by integrating calibration and error detection and correction, such as distributed offset calibration and redundant comparators. Power and area requirements are dramatically reduced by using low BER rectification to nearly halve the number of comparators in a conventional high speed, low BER flash ADC.

Abstract translation: 描述了具有模数转换器（ADC）的DSP接收机的方法和装置，具有高速度，低BER性能，低功率和面积要求。 通过解决传统的瓶颈，提高了多路径ADC配置的速度。 通过集成校准和错误检测和校正（例如分布式偏移校准和冗余比较器）来提高ADC性能。 通过使用低BER整流将传统高速，低BER闪存ADC中的比较器数量减半，功率和面积要求大大降低。

公开(公告)号：US20130270674A1

公开(公告)日：2013-10-17

申请号：US13918826

申请日：2013-06-14

Applicant: Broadcom Corporation

Inventor： Hooman DARABI ,  Qiang LI ,  Bo Zhang

IPC: H01L49/02

CPC classification number: H01L28/40 ,  H01L23/5223 ,  H01L27/0805 ,  H01L28/87 ,  H01L28/91 ,  H01L29/93 ,  H01L29/94 ,  H01L2924/0002 ,  H01L2924/00

Abstract: At least a first capacitor is formed on a substrate and connected to a first differential node of a differential circuit, and the first capacitor may be variable in capacitance. A second capacitor is formed on the substrate and connected to a second differential node of the differential circuit, and the second capacitor also may be variable. A third capacitor is connected between the first differential node and the second differential node, and is formed at least partially above the first capacitor. In this way, a size of the first capacitor and/or the second capacitor may be reduced on the substrate, and capacitances of the first and/or second capacitor(s) may be adjusted in response to a variable characteristic of one or more circuit components of the differential circuit.

Abstract translation: 至少第一电容器形成在衬底上并连接到差分电路的第一差分节点，并且第一电容器可以是可变电容的。 第二电容器形成在衬底上并连接到差分电路的第二差分节点，并且第二电容器也可以是可变的。 第三电容器连接在第一差分节点和第二差分节点之间，并且至少部分地形成在第一电容器的上方。 以这种方式，可以在衬底上减小第一电容器和/或第二电容器的尺寸，并且可以响应于一个或多个电路的可变特性来调整第一和/或第二电容器的电容 差分电路的组件。