公开(公告)号：US09246670B2

公开(公告)日：2016-01-26

申请号：US14637306

申请日：2015-03-03

申请人： BROADCOM CORPORATION

发明人： Mahmoud Reza Ahmadi ,  Siavash Fallahi ,  Tamer Ali ,  Ali Nazemi ,  Hassan Maarefi ,  Burak Catli ,  Afshin Momtaz

IPC分类号： H04L7/033 ,  H03L7/00 ,  H03L7/099 ,  H04L7/00

CPC分类号： H04L7/0331 ,  H03L7/00 ,  H03L7/0996 ,  H04L7/0016

摘要： A high-speed clock generator device includes a phase-interpolator (PI) circuit, a smoothing block, and inverter-based low-pass filters. The PI circuit receives a multiple clock signals with different phase angles and generates an output clock signal having a correct phase angle. The smoothing block smooths the clock signals with different phase angles and generates a number of smooth clock signals featuring improved linearity. The inverter-based low-pass filters filter harmonics of the clock signals with different phase angles.

摘要翻译： 高速时钟发生器装置包括相位插值器（PI）电路，平滑块和基于反相器的低通滤波器。 PI电路接收具有不同相位角的多个时钟信号，并产生具有正确相位角的输出时钟信号。 平滑块平滑具有不同相位角的时钟信号，并产生许多具有改进线性度的平滑时钟信号。 基于逆变器的低通滤波器滤波具有不同相位角的时钟信号的谐波。

公开(公告)号：US09184737B1

公开(公告)日：2015-11-10

申请号：US14332106

申请日：2014-07-15

申请人： Broadcom Corporation

发明人： Tamer Ali ,  Jun Cao

IPC分类号： H03M1/10 ,  H03K5/135 ,  H03M1/12

CPC分类号： H04B17/21 ,  H03K5/135 ,  H03M1/1023 ,  H03M1/1215 ,  H03M1/1245 ,  H04L7/0012

摘要： A device includes process mitigating timing (PMT) circuitry. The PMT circuitry allows for adjustment of a clock signal while compensating for process variation within the PMT circuitry. The PMT circuitry may include process mitigating buffer (PMB) circuitry. The PMB circuitry may utilize replica circuitry and a calibrated resistance to generate a calibrated bias voltage. The calibrated bias voltage may be used to drive component buffer circuits to create a calibrated current response. The calibrated current response may correspond to a selected output impedance for the component buffer circuits. The select output impedance may be used in concert with a variable capacitance to adjust a clock signal in manner that is independent of the process variation within the PMT circuitry.

摘要翻译： 一种设备包括进程减轻时序（PMT）电路。 PMT电路允许调整时钟信号，同时补偿PMT电路内的过程变化。 PMT电路可以包括过程减缓缓冲器（PMB）电路。 PMB电路可以利用复制电路和经校准的电阻来产生校准偏置电压。 校准的偏置电压可用于驱动元件缓冲器电路以产生校准的电流响应。 校准的电流响应可以对应于组件缓冲器电路的选择的输出阻抗。 选择输出阻抗可以与可变电容一起使用，以独立于PMT电路内的过程变化的方式调整时钟信号。

公开(公告)号：US20140146922A1

公开(公告)日：2014-05-29

申请号：US13720623

申请日：2012-12-19

申请人： BROADCOM CORPORATION

发明人： Ali Nazemi ,  Mahmoud Reza Ahmadi ,  Tamer Ali ,  Bo Zhang ,  Mohammed Abdul-Latif ,  Namik Kocaman ,  Afshin Momtaz

IPC分类号： H04L25/02

CPC分类号： H04L7/00 ,  H04L7/002 ,  H04L25/0272 ,  H04L25/0292 ,  H04L25/0296 ,  H04L25/06

摘要： Techniques are described herein that provide an interface for receiving and deserializing digital bit stream(s). For instance, a receiver for a high-speed deserializer may include digital slicers, a digital phase interpolator, and a digital clock phase generator. The digital slicers may be configured to determine a digital value of a data input. The digital phase interpolator may be configured to generate an interpolated clock signal based on input clock signals that correspond to respective phases of a reference clock. The phase of the interpolated clock tracks the data input to the receiver through a clock recovery loop. The digital clock phase generator may be configured to generate output clock signals to control timing of the respective digital slicers. The receiver may further include a single digital eye monitor configured to monitor a data eye of the data input.

摘要翻译： 这里描述了提供用于接收和反序列化数字比特流的接口的技术。 例如，用于高速解串器的接收器可以包括数字限幅器，数字相位内插器和数字时钟相位发生器。 数字限幅器可以被配置为确定数据输入的数字值。 数字相位插值器可以被配置为基于对应于参考时钟的各个相位的输入时钟信号来产生内插时钟信号。 内插时钟的相位通过时钟恢复循环跟踪输入到接收器的数据。 数字时钟相位发生器可以被配置为产生输出时钟信号以控制各个数字限幅器的定时。 接收器还可以包括被配置为监视数据输入的数据眼睛的单个数字眼睛监视器。

公开(公告)号：US09503114B1

公开(公告)日：2016-11-22

申请号：US14855026

申请日：2015-09-15

申请人： Broadcom Corporation

发明人： Tamer Ali ,  Ramy Mohamed Yousry Ahmed Elsayed Awad ,  Jun Cao

IPC分类号： H03M1/06 ,  H03M1/12 ,  H03M1/36

CPC分类号： H03M1/1245 ,  H03M1/1215

摘要： A multi-lane analog to digital converter (ADC) samples an analog input according to multiple phases of a sampling clock. Ideally, the multiple phases of the sampling clock are non-overlapping. The multi-lane ADC includes one or more reset switches to remove any residual samples that can remain after their conversion from an analog signal domain to a digital signal domain. As a result of this removal, the multiple phases of the sampling clock need not to ideally coincide with one other. Rather, some overlap between the multiple phases of the sampling clock can exist while having digital output samples still accurately represent the analog input.

摘要翻译： 多通道模数转换器（ADC）根据采样时钟的多个相位对模拟输入采样。 理想情况下，采样时钟的多个相位是不重叠的。 多通道ADC包括一个或多个复位开关，以去除在从模拟信号域转换为数字信号域之后可以保留的任何残留样本。 作为这种去除的结果，采样时钟的多个阶段不需要理想地彼此重合。 相反，采样时钟的多个相位之间可能存在一些重叠，同时数字输出采样仍然准确地表示模拟输入。

公开(公告)号：US20160036538A1

公开(公告)日：2016-02-04

申请号：US14882980

申请日：2015-10-14

申请人： Broadcom Corporation

发明人： Tamer Ali ,  Jun Cao

IPC分类号： H04B17/21 ,  H04L7/00

CPC分类号： H04B17/21 ,  H03K5/135 ,  H03M1/1023 ,  H03M1/1215 ,  H03M1/1245 ,  H04L7/0012

摘要： A device includes process mitigating timing (PMT) circuitry. The PMT circuitry allows for adjustment of a clock signal while compensating for process variation within the PMT circuitry. The PMT circuitry may include process mitigating buffer (PMB) circuitry. The PMB circuitry may utilize replica circuitry and a calibrated resistance to generate a calibrated bias voltage. The calibrated bias voltage may be used to drive component buffer circuits to create a calibrated current response. The calibrated current response may correspond to a selected output impedance for the component buffer circuits. The select output impedance may be used in concert with a variable capacitance to adjust a clock signal in manner that is independent of the process variation within the PMT circuitry.

摘要翻译： 一种设备包括进程减轻时序（PMT）电路。 PMT电路允许调整时钟信号，同时补偿PMT电路内的过程变化。 PMT电路可以包括过程减缓缓冲器（PMB）电路。 PMB电路可以利用复制电路和经校准的电阻来产生校准偏置电压。 校准的偏置电压可用于驱动元件缓冲器电路以产生校准的电流响应。 校准的电流响应可以对应于组件缓冲器电路的选择的输出阻抗。 选择输出阻抗可以与可变电容一起使用，以独立于PMT电路内的过程变化的方式调整时钟信号。

公开(公告)号：US09001869B2

公开(公告)日：2015-04-07

申请号：US13946981

申请日：2013-07-19

申请人： Broadcom Corporation

发明人： Mahmoud Reza Ahmadi ,  Siavash Fallahi ,  Tamer Ali ,  Ali Nazemi ,  Hassan Maarefi ,  Burak Catli ,  Afshin Momtaz

IPC分类号： H04B3/36 ,  H03L7/00

CPC分类号： H04L7/0331 ,  H03L7/00 ,  H03L7/0996 ,  H04L7/0016

摘要： A device for high-speed clock generation may include an injection locking-ring oscillator (ILRO) configured to receive one or more input clock signals and to generate multiple clock signals with different equally spaced phase angles. A phase-interpolator (PI) circuit may be configured to receive the multiple coarse spaced clock signals and to generate an output clock signal having a correct phase angle. The PI circuit may include a smoothing block that may be configured to smooth the multiple clock signals with different phase angles and to generate multiple smooth clock signals. A pulling block may be configured to pull edges of the multiple smooth clock signals closer to one another.

摘要翻译： 用于高速时钟产生的装置可以包括被配置为接收一个或多个输入时钟信号并且生成具有不同等间隔的相位角的多个时钟信号的注入锁定环形振荡器（ILRO）。 相位插值器（PI）电路可以被配置为接收多个粗略间隔的时钟信号并且产生具有正确相位角的输出时钟信号。 PI电路可以包括平滑块，其可以被配置为平滑具有不同相位角的多个时钟信号并且生成多个平滑时钟信号。 牵引块可以被配置成拉近多个平滑时钟信号的边缘彼此更接近。

公开(公告)号：US08994399B2

公开(公告)日：2015-03-31

申请号：US13897314

申请日：2013-05-17

申请人： Broadcom Corporation

发明人： Tamer Ali

IPC分类号： H03K17/16 ,  H03H11/30 ,  H03K19/0185 ,  H04L25/02

CPC分类号： H03H11/30 ,  H03K19/018571 ,  H04L25/0298

摘要： A transmission line driver including an output configured to have a load impedance is provided. The transmission line driver includes a pull-up circuit coupled in series with the output. The transmission line driver also includes a pull-down circuit coupled in series with the output. The transmission line driver includes a shunt circuit having an adjustable impedance. The shunt circuit is coupled in parallel to the output. The shunt circuit is coupled to the pull-up circuit and the pull-down circuit. The shunt circuit is configured to receive a shunt control signal to adjust the adjustable impedance to provide linear control of an output swing at the output.

摘要翻译： 提供包括配置为具有负载阻抗的输出的传输线驱动器。 传输线驱动器包括与输出串联耦合的上拉电路。 传输线驱动器还包括与输出串联耦合的下拉电路。 传输线驱动器包括具有可调阻抗的分流电路。 并联电路与输出端并联。 分流电路耦合到上拉电路和下拉电路。 分流电路被配置为接收分流控制信号以调节可调阻抗以提供对输出端的输出摆幅的线性控制。

公开(公告)号：US20140241442A1

公开(公告)日：2014-08-28

申请号：US13946981

申请日：2013-07-19

申请人： BROADCOM CORPORATION

发明人： Mahmoud Reza Ahmadi ,  Siavash Fallahi ,  Tamer Ali ,  Ali Nazemi ,  Hassan Maarefi ,  Burak Catli ,  Afshin Momtaz

IPC分类号： H03L7/00

CPC分类号： H04L7/0331 ,  H03L7/00 ,  H03L7/0996 ,  H04L7/0016

摘要： A device for high-speed clock generation may include an injection locking-ring oscillator (ILRO) configured to receive one or more input clock signals and to generate multiple clock signals with different equally spaced phase angles. A phase-interpolator (PI) circuit may be configured to receive the multiple coarse spaced clock signals and to generate an output clock signal having a correct phase angle. The PI circuit may include a smoothing block that may be configured to smooth the multiple clock signals with different phase angles and to generate multiple smooth clock signals. A pulling block may be configured to pull edges of the multiple smooth clock signals closer to one another.

摘要翻译： 用于高速时钟产生的装置可以包括被配置为接收一个或多个输入时钟信号并且生成具有不同等间隔的相位角的多个时钟信号的注入锁定环形振荡器（ILRO）。 相位插值器（PI）电路可以被配置为接收多个粗略间隔的时钟信号并且产生具有正确相位角的输出时钟信号。 PI电路可以包括平滑块，其可以被配置为平滑具有不同相位角的多个时钟信号并且生成多个平滑时钟信号。 牵引块可以被配置成拉近多个平滑时钟信号的边缘彼此更接近。

公开(公告)号：US09024659B2

公开(公告)日：2015-05-05

申请号：US14072641

申请日：2013-11-05

申请人： Broadcom Corporation

发明人： Tamer Ali ,  Hassan Maarefi ,  Mahmoud Reza Ahmadi ,  Afshin Momtaz

IPC分类号： H03K19/094 ,  H03K17/16 ,  H04L25/03

CPC分类号： H04L25/03019 ,  H04L25/0288 ,  H04L25/03885 ,  H04L2025/03471 ,  H04L2025/03681

摘要： A device for passive equalization and slew-rate control of a signal includes a first branch and a second branch. The first branch includes a first driver coupled in series with an equalization capacitor. The second branch includes a second driver coupled in series with a resistor. The second branch may be coupled in parallel to the first branch. The first branch may be configurable to enable either passive equalization or slew-rate control of the signal based on a mode control signal.

摘要翻译： 用于信号的无源均衡和转换速率控制的装置包括第一分支和第二分支。 第一分支包括与均衡电容器串联耦合的第一驱动器。 第二分支包括与电阻器串联耦合的第二驱动器。 第二分支可以与第一分支并联耦合。 第一分支可以被配置为基于模式控制信号实现对信号的无源均衡或转换速率控制。

公开(公告)号：US08958501B2

公开(公告)日：2015-02-17

申请号：US13720623

申请日：2012-12-19

申请人： Broadcom Corporation

发明人： Ali Nazemi ,  Mahmoud Reza Ahmadi ,  Tamer Ali ,  Bo Zhang ,  Mohammed Abdul-Latif ,  Namik Kocaman ,  Afshin Momtaz

IPC分类号： H03K9/00 ,  H04L7/00 ,  H04L25/02 ,  H04L25/06

CPC分类号： H04L7/00 ,  H04L7/002 ,  H04L25/0272 ,  H04L25/0292 ,  H04L25/0296 ,  H04L25/06

摘要： Techniques are described herein that provide an interface for receiving and deserializing digital bit stream(s). For instance, a receiver for a high-speed deserializer may include digital slicers, a digital phase interpolator, and a digital clock phase generator. The digital slicers may be configured to determine a digital value of a data input. The digital phase interpolator may be configured to generate an interpolated clock signal based on input clock signals that correspond to respective phases of a reference clock. The phase of the interpolated clock tracks the data input to the receiver through a clock recovery loop. The digital clock phase generator may be configured to generate output clock signals to control timing of the respective digital slicers. The receiver may further include a single digital eye monitor configured to monitor a data eye of the data input.

摘要翻译： 这里描述了提供用于接收和反序列化数字比特流的接口的技术。 例如，用于高速解串器的接收器可以包括数字限幅器，数字相位内插器和数字时钟相位发生器。 数字限幅器可以被配置为确定数据输入的数字值。 数字相位插值器可以被配置为基于对应于参考时钟的各个相位的输入时钟信号来产生内插时钟信号。 内插时钟的相位通过时钟恢复循环跟踪输入到接收器的数据。 数字时钟相位发生器可以被配置为产生输出时钟信号以控制各个数字限幅器的定时。 接收器还可以包括被配置为监视数据输入的数据眼睛的单个数字眼睛监视器。