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1.发明授权公开(公告)号：US08873606B2
公开(公告)日：2014-10-28
申请号：US13671340
申请日：2012-11-07
Applicant: Broadcom Corporation
Inventor： Heng Zhang , Mehdi Khanpour , Jun Cao , Chang Liu , Afshin Momtaz
Abstract: Methods, systems, and apparatuses are described for reducing the latency in a transceiver. A transceiver includes a high latency communication channel and a low latency communication channel that is configured to be a bypass channel for the high latency communication channel. The low latency communication channel may be utilized when implementing the transceiver is used in low latency applications. By bypassing the high latency communication channel, the high latency that is introduced therein (due to the many stages of de-serialization used to reduce the data rate for digital processing) can be avoided. An increase in data rate is realized when the low latency communication channel is used to pass data. A delay-locked loop (DLL) may be used to phase align the transmitter clock of the transceiver with the receiver clock of the transceiver to compensate for a limited tolerance of phase offset between these clocks.
Abstract translation: 描述了减少收发器中的延迟的方法，系统和装置。 收发器包括高延迟通信信道和被配置为高延迟通信信道的旁路信道的低延迟通信信道。 当在低延迟应用中使用收发器时，可以利用低延迟通信信道。 通过绕过高延迟通信信道，可以避免其中引入的高等待时间（由于用于减少数字处理的数据速率的许多解除序列化阶段）。 当低延迟通信信道用于传递数据时，实现数据速率的增加。 可以使用延迟锁定环（DLL）将收发器的发射机时钟与收发器的接收机时钟相位对准，以补偿这些时钟之间的相位偏移的有限公差。
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Patent Agency Ranking
2.发明授权公开(公告)号：US09306621B2
公开(公告)日：2016-04-05
申请号：US14498383
申请日：2014-09-26
Applicant: Broadcom Corporation
Inventor： Heng Zhang , Mehdi Khanpour , Jun Cao , Chang Liu , Afshin Momtaz
Abstract: Methods, systems, and apparatuses are described for reducing the latency in a transceiver. A transceiver includes a high latency communication channel and a low latency communication channel that is configured to be a bypass channel for the high latency communication channel. The low latency communication channel may be utilized when implementing the transceiver is used in low latency applications. By bypassing the high latency communication channel, the high latency that is introduced therein (due to the many stages of de-serialization used to reduce the data rate for digital processing) can be avoided. An increase in data rate is realized when the low latency communication channel is used to pass data. A delay-locked loop (DLL) may be used to phase align the transmitter clock of the transceiver with the receiver clock of the transceiver to compensate for a limited tolerance of phase offset between these clocks.
Abstract translation: 描述了减少收发器中的延迟的方法，系统和装置。 收发器包括高延迟通信信道和被配置为高延迟通信信道的旁路信道的低延迟通信信道。 当在低延迟应用中使用收发器时，可以利用低延迟通信信道。 通过绕过高延迟通信信道，可以避免其中引入的高等待时间（由于用于减少数字处理的数据速率的许多解除序列化阶段）。 当低延迟通信信道用于传递数据时，实现数据速率的增加。 可以使用延迟锁定环（DLL）将收发器的发射机时钟与收发器的接收机时钟相位对准，以补偿这些时钟之间的相位偏移的有限公差。
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3.发明申请公开(公告)号：US20150010044A1
公开(公告)日：2015-01-08
申请号：US14498383
申请日：2014-09-26
Applicant: Broadcom Corporation
Inventor： Heng Zhang , Mehdi Khanpour , Jun Cao , Chang Liu , Afshin Momtaz
Abstract: Methods, systems, and apparatuses are described for reducing the latency in a transceiver. A transceiver includes a high latency communication channel and a low latency communication channel that is configured to be a bypass channel for the high latency communication channel. The low latency communication channel may be utilized when implementing the transceiver is used in low latency applications. By bypassing the high latency communication channel, the high latency that is introduced therein (due to the many stages of de-serialization used to reduce the data rate for digital processing) can be avoided. An increase in data rate is realized when the low latency communication channel is used to pass data. A delay-locked loop (DLL) may be used to phase align the transmitter clock of the transceiver with the receiver clock of the transceiver to compensate for a limited tolerance of phase offset between these clocks.
Abstract translation: 描述了减少收发器中的延迟的方法，系统和装置。 收发器包括高延迟通信信道和被配置为高延迟通信信道的旁路信道的低延迟通信信道。 当在低延迟应用中使用收发器时，可以利用低延迟通信信道。 通过绕过高延迟通信信道，可以避免其中引入的高等待时间（由于用于减少数字处理的数据速率的许多解除序列化阶段）。 当低延迟通信信道用于传递数据时，实现数据速率的增加。 可以使用延迟锁定环（DLL）将收发器的发射机时钟与收发器的接收机时钟相位对准，以补偿这些时钟之间的相位偏移的有限公差。
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公开(公告)号：US08947167B2
公开(公告)日：2015-02-03
申请号：US13931189
申请日：2013-06-28
Applicant: Broadcom Corporation
Inventor： Mahyar Kargar , Siavash Fallahi , Namik Kocaman , Mehdi Khanpour , Afshin Momtaz
CPC classification number: G01R23/02 , G01R23/15 , G01R25/00 , H03D13/00 , H03L7/00 , H03L7/0807 , H03L7/091 , H03L7/113 , H03L2207/06
Abstract: Embodiments provide a reference-less frequency detector that overcomes the “dead zone” problem of conventional circuits. In particular, the frequency detector is able to accurately resolve the polarity of the frequency difference between the VCO clock signal and the data signal, irrespective of the magnitude of the frequency difference and the presence of VCO clock jitter and/or ISI on the data signal.
Abstract translation: 实施例提供了一种克服常规电路的“死区”问题的无参考频率检测器。 特别地，频率检测器能够精确地解决VCO时钟信号和数据信号之间的频率差的极性，而不管频率差的大小和数据信号上是否存在VCO时钟抖动和/或ISI 。
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5.发明申请公开(公告)号：US20140126613A1
公开(公告)日：2014-05-08
申请号：US13671340
申请日：2012-11-07
Applicant: BROADCOM CORPORATION
Inventor： Heng Zhang , Mehdi Khanpour , Jun Cao , Chang Liu , Afshin Momtaz
IPC: H03D3/02
Abstract: Methods, systems, and apparatuses are described for reducing the latency in a transceiver. A transceiver includes a high latency communication channel and a low latency communication channel that is configured to be a bypass channel for the high latency communication channel. The low latency communication channel may be utilized when implementing the transceiver is used in low latency applications. By bypassing the high latency communication channel, the high latency that is introduced therein (due to the many stages of de-serialization used to reduce the data rate for digital processing) can be avoided. An increase in data rate is realized when the low latency communication channel is used to pass data. A delay-locked loop (DLL) may be used to phase align the transmitter clock of the transceiver with the receiver clock of the transceiver to compensate for a limited tolerance of phase offset between these clocks.
Abstract translation: 描述了减少收发器中的延迟的方法，系统和装置。 收发器包括高延迟通信信道和被配置为高延迟通信信道的旁路信道的低延迟通信信道。 当在低延迟应用中使用收发器时，可以利用低延迟通信信道。 通过绕过高延迟通信信道，可以避免其中引入的高等待时间（由于用于减少数字处理的数据速率的许多解除序列化阶段）。 当低延迟通信信道用于传递数据时，实现数据速率的增加。 可以使用延迟锁定环（DLL）将收发器的发射机时钟与收发器的接收机时钟相位对准，以补偿这些时钟之间的相位偏移的有限公差。
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公开(公告)号：US20130285752A1
公开(公告)日：2013-10-31
申请号：US13931189
申请日：2013-06-28
Applicant: Broadcom Corporation
Inventor： Mahyar KARGAR , Siavash Fallahi , Namik Kocaman , Mehdi Khanpour , Afshin Momtaz
CPC classification number: G01R23/02 , G01R23/15 , G01R25/00 , H03D13/00 , H03L7/00 , H03L7/0807 , H03L7/091 , H03L7/113 , H03L2207/06
Abstract: Embodiments provide a reference-less frequency detector that overcomes the “dead zone” problem of conventional circuits. In particular, the frequency detector is able to accurately resolve the polarity of the frequency difference between the VCO clock signal and the data signal, irrespective of the magnitude of the frequency difference and the presence of VCO clock jitter and/or ISI on the data signal.
Abstract translation: 实施例提供了一种克服常规电路的“死区”问题的无参考频率检测器。 特别地，频率检测器能够精确地解决VCO时钟信号和数据信号之间的频率差的极性，而不管频率差的大小和数据信号上是否存在VCO时钟抖动和/或ISI 。
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