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    Method for fabricating isolated integrated semiconductor structures
    1.
    发明授权
    Method for fabricating isolated integrated semiconductor structures 有权
    隔离集成半导体结构的制造方法

    公开(公告)号：US08012842B2

    公开(公告)日：2011-09-06

    申请号：US12137817

    申请日：2008-06-12

    申请人： Scott Balster ,  Badih El-Kareh ,  Hiroshi Yasuda

    发明人： Scott Balster ,  Badih El-Kareh ,  Hiroshi Yasuda

    IPC分类号： H01L21/331

    CPC分类号： H01L27/0623 ,  H01L21/82285 ,  H01L21/8249 ,  H01L21/84 ,  H01L27/0826 ,  H01L27/1203

    摘要： An integrated semiconductor structure that has first and second bipolar transistor structures. The first bipolar transistor structure has a doped tank region in contact with a doped tank region located underneath a contacting sinker. The second bipolar transistor structure has a doped buried region that is the same dopant type as its doped tank region. A method for fabricating an integrated semiconductor structure in a bulk semiconductor wafer. A first patterned photomask is used to form a doped buried region and a doped tank region within the first bipolar transistor structure. A second patterned photomask is used to form a doped buried region and a doped tank region within the second bipolar transistor, plus a doped buried region and a doped tank region underneath a contacting sinker adjacent to the first bipolar transistor.

    摘要翻译： 具有第一和第二双极晶体管结构的集成半导体结构。 第一双极晶体管结构具有与位于接触沉降片下方的掺杂槽区接触的掺杂槽区。 第二双极晶体管结构具有与其掺杂槽区相同的掺杂剂类型的掺杂掩埋区。 一种用于在体半导体晶片中制造集成半导体结构的方法。 第一图案化光掩模用于在第一双极晶体管结构内形成掺杂掩埋区和掺杂槽区。 第二图案化光掩模用于在第二双极晶体管内形成掺杂掩埋区和掺杂槽区，加上与第一双极晶体管相邻的接触沉积片下方的掺杂掩埋区和掺杂槽区。

    Method of Fabricating an Integrated Circuit with Gate Self-Protection, and an Integrated Circuit with Gate Self-Protection
    2.
    发明申请
    Method of Fabricating an Integrated Circuit with Gate Self-Protection, and an Integrated Circuit with Gate Self-Protection 有权
    具有栅极自保护的集成电路的制造方法以及具有栅极自保护的集成电路

    公开(公告)号：US20070057281A1

    公开(公告)日：2007-03-15

    申请号：US11470760

    申请日：2006-09-07

    申请人： Badih El-Kareh ,  Scott Balster ,  Hiroshi Yasuda ,  Manfred Schiekofer

    发明人： Badih El-Kareh ,  Scott Balster ,  Hiroshi Yasuda ,  Manfred Schiekofer

    IPC分类号： H01L29/74

    CPC分类号： H01L27/0623 ,  H01L21/8249 ,  H01L27/0251 ,  H01L27/0705

    摘要： An integrated circuit with gate self-protection comprises a MOS device and a bipolar device, wherein the integrated circuit further comprises a semiconductor layer with electrically active regions in which and on which the MOS device and the bipolar device are formed and electrically inactive regions for isolating the electrically active regions from each other. The MOS device comprises a gate structure and a body contacting structure, wherein the body contacting structure is formed of a base layer deposited in a selected region over an electrically active region of the semiconductor layer, and the body contacting structure is electrically connected with the gate structure. The base layer forming the body contacting structure also forms the base of the bipolar device. The present invention further relates to a method for fabricating such an integrated circuit.

    摘要翻译： 具有栅极自保护的集成电路包括MOS器件和双极器件，其中所述集成电路还包括具有电活性区域的半导体层，在其上形成MOS器件和双极器件，并且在其上形成用于隔离的电无活性区域 电活性区域彼此。 MOS器件包括栅极结构和体接触结构，其中所述体接触结构由沉积在所述半导体层的电活性区域上的选定区域中的基底层形成，并且所述体接触结构与所述栅极电连接 结构体。 形成身体接触结构的基层也形成双极器件的基部。 本发明还涉及一种用于制造这种集成电路的方法。

    Semiconductor device having a first bipolar device and a second bipolar device and method for fabrication
    3.
    发明授权
    Semiconductor device having a first bipolar device and a second bipolar device and method for fabrication 有权
    具有第一双极器件和第二双极器件的半导体器件及其制造方法

    公开(公告)号：US08450179B2

    公开(公告)日：2013-05-28

    申请号：US11670729

    申请日：2007-02-02

    申请人： Badih El-Kareh ,  Hiroshi Yasuda ,  Scott Balster

    发明人： Badih El-Kareh ,  Hiroshi Yasuda ,  Scott Balster

    IPC分类号： H01L21/331

    CPC分类号： H01L29/7378 ,  H01L21/8222 ,  H01L21/8249 ,  H01L27/0825 ,  H01L29/66242

    摘要： A method for fabricating a semiconductor device having a first and second bipolar devices of the same dopant type includes: depositing a dielectric layer over a semiconductor layer, depositing a gate conductor layer over the dielectric layer, defining base regions of both bipolar devices, removing the gate conductor layer and dielectric layer in the base regions, depositing a base layer on the gate conductor layer and on the exposed semiconductor layer in the base regions, depositing an insulating layer over the base layer, forming a photoresist layer and defining emitter regions of both bipolar devices, removing the photoresist layer in the emitter regions thereby forming two emitter windows, masking the emitter window of the first bipolar device and exposing the base layer in the base region of the second bipolar device to an additional emitter implant through the associated emitter window.

    摘要翻译： 一种用于制造具有相同掺杂剂类型的第一和第二双极器件的半导体器件的方法包括：在半导体层上沉积介电层，在电介质层上沉积栅极导体层，限定两个双极器件的基极区域， 栅极导体层和电介质层，在栅极导体层和基极区域的暴露的半导体层上沉积基底层，在基底层上沉积绝缘层，形成光致抗蚀剂层并限定两者的发射极区域 去除发射极区域中的光致抗蚀剂层，从而形成两个发射器窗口，掩蔽第一双极器件的发射极窗口，并将第二双极器件的基极区域中的基极层通过相关的发射极窗口暴露于另外的发射体注入 。

    SEMICONDUCTOR DEVICE HAVING A FIRST BIPOLAR DEVICE AND A SECOND BIPOLAR DEVICE AND METHOD FOR FABRICATION
    6.
    发明申请
    SEMICONDUCTOR DEVICE HAVING A FIRST BIPOLAR DEVICE AND A SECOND BIPOLAR DEVICE AND METHOD FOR FABRICATION 有权
    具有第一双极器件的第二半导体器件和第二双极器件及其制造方法

    公开(公告)号：US20070207585A1

    公开(公告)日：2007-09-06

    申请号：US11670729

    申请日：2007-02-02

    申请人： Badih El-Kareh ,  Hiroshi Yasuda ,  Scott Balster

    发明人： Badih El-Kareh ,  Hiroshi Yasuda ,  Scott Balster

    IPC分类号： H01L21/331

    CPC分类号： H01L29/7378 ,  H01L21/8222 ,  H01L21/8249 ,  H01L27/0825 ,  H01L29/66242

    摘要： A method of fabricating a BiCMOS device comprising a first bipolar device and a second bipolar device being of the same dopant type and a BiCMOS device comprising a first bipolar device and a second bipolar device being of the same dopant type A method for fabricating a BICMOS device comprising a first bipolar device and a second bipolar device being of the same dopant type comprises the steps of depositing a dielectric layer (24) over a semiconductor layer (14), depositing a gate conductor layer (26) over the dielectric layer (24), defining base regions (28, 30) of the first and second bipolar devices; removing the gate conductor layer (26) and the dielectric layer (24) in the base regions (28, 30) of the first and second bipolar devices, depositing a base layer (32) on the gate conductor layer (26) and on the exposed semiconductor layer (14) in the base regions (28, 30) of the first and second bipolar devices depositing an insulating layer (36) over said base layer (32), forming a photoresist layer (38) and defining emitter regions (40, 42) of the first and second bipolar devices, removing the photoresist layer (38) in the emitter regions (40, 42) of the first and second bipolar devices thereby forming two emitter windows (44, 46), masking the emitter window (44) of the first bipolar device and exposing said base layer (32) in the base region (30) of the second bipolar device to an additional emitter implant through the associated emitter window (46).

    摘要翻译： 一种制造BiCMOS器件的方法，其包括具有相同掺杂剂类型的第一双极器件和第二双极器件，以及包括第一双极器件和第二双极器件的BiCMOS器件，其具有相同的掺杂剂A型制造BICMOS器件的方法 包括第一双极器件和具有相同掺杂剂类型的第二双极器件包括以下步骤：在半导体层（14）上沉积介电层（24），在电介质层（24）上沉积栅极导体层（26） 限定第一和第二双极器件的基极区域（28,30）; 去除第一和第二双极器件的基极区域（28,30）中的栅极导体层（26）和介电层（24），在栅极导体层（26）上沉积基极层（32） 在所述第一和第二双极器件的基极区（28,30）中暴露的半导体层（14）在所述基极层（32）上沉积绝缘层（36），形成光致抗蚀剂层（38）并限定发射极区域 ，42），去除第一和第二双极器件的发射极区域（40,42）中的光致抗蚀剂层（38），从而形成两个发射器窗口（44,46），掩蔽发射器窗口 44），并且通过所述相关联的发射器窗（46）将所述第二双极器件的基极区域（30）中的所述基极层（32）暴露于另外的发射体注入。

    Method of fabricating an integrated circuit with gate self-protection, and an integrated circuit with gate self-protection
    7.
    发明授权
    Method of fabricating an integrated circuit with gate self-protection, and an integrated circuit with gate self-protection 有权
    具有栅极自保护的集成电路的制造方法和具有栅极自保护的集成电路

    公开(公告)号：US07772057B2

    公开(公告)日：2010-08-10

    申请号：US11470760

    申请日：2006-09-07

    申请人： Badih El-Kareh ,  Scott Gerard Balster ,  Hiroshi Yasuda ,  Manfred Schiekofer

    发明人： Badih El-Kareh ,  Scott Gerard Balster ,  Hiroshi Yasuda ,  Manfred Schiekofer

    IPC分类号： H01L21/337

    CPC分类号： H01L27/0623 ,  H01L21/8249 ,  H01L27/0251 ,  H01L27/0705

    摘要： An integrated circuit with gate self-protection comprises a MOS device and a bipolar device, wherein the integrated circuit further comprises a semiconductor layer with electrically active regions in which and on which the MOS device and the bipolar device are formed and electrically inactive regions for isolating the electrically active regions from each other. The MOS device comprises a gate structure and a body contacting structure, wherein the body contacting structure is formed of a base layer deposited in a selected region over an electrically active region of the semiconductor layer, and the body contacting structure is electrically connected with the gate structure. The base layer forming the body contacting structure also forms the base of the bipolar device. The present invention further relates to a method for fabricating such an integrated circuit.

    摘要翻译： 具有栅极自保护的集成电路包括MOS器件和双极器件，其中所述集成电路还包括具有电活性区域的半导体层，在其上形成MOS器件和双极器件，并且在其上形成用于隔离的电无活性区域 电活性区域彼此。 MOS器件包括栅极结构和体接触结构，其中所述体接触结构由沉积在所述半导体层的电活性区域上的选定区域中的基底层形成，并且所述体接触结构与所述栅极电连接 结构体。 形成身体接触结构的基层也形成双极器件的基部。 本发明还涉及一种用于制造这种集成电路的方法。

    Open source/drain junction field effect transistor
    9.
    发明授权
    Open source/drain junction field effect transistor 有权
    开路/漏极结场效应晶体管

    公开(公告)号：US07615425B2

    公开(公告)日：2009-11-10

    申请号：US11504412

    申请日：2006-08-15

    申请人： Joe R. Trogolo ,  Hiroshi Yasuda ,  Badih El-Kareh ,  Philipp Steinmann

    发明人： Joe R. Trogolo ,  Hiroshi Yasuda ,  Badih El-Kareh ,  Philipp Steinmann

    IPC分类号： H01L21/337

    CPC分类号： H01L29/808 ,  H01L29/0607 ,  H01L29/66901

    摘要： The disclosure herein pertains to fashioning an n channel junction field effect transistor (NJFET) and/or a p channel junction field effect transistor (PJFET) with an open drain, where the open drain allows the transistors to operate at higher voltages before experiencing gate leakage current. The open drain allows the voltage to be increased several fold without increasing the size of the transistors. Opening the drain essentially spreads equipotential lines of respective electric fields developed at the drains of the devices so that the local electric fields, and hence the impact ionization rates are reduced to redirect current below the surface of the transistors.

    摘要翻译： 本文的公开内容涉及具有开路漏极的n沟道结场效应晶体管（NJFET）和/或ap沟道结场效应晶体管（PJFET），其中开路漏极允许晶体管在经历栅极漏电流之前以更高的电压工作 。 开路漏极允许电压增加几倍，而不增加晶体管的尺寸。 开放漏极基本上扩散了在器件的漏极处产生的相应电场的等势线，使得局部电场以及因此的冲击电离率被降低以将电流重新导向晶体管表面以下。

    Open source/drain junction field effect transistor
    10.
    发明申请
    Open source/drain junction field effect transistor 有权
    开路/漏极结场效应晶体管

    公开(公告)号：US20080042199A1

    公开(公告)日：2008-02-21

    申请号：US11504412

    申请日：2006-08-15

    申请人： Joe R. Trogolo ,  Hiroshi Yasuda ,  Badih El-Kareh ,  Philipp Steinmann

    发明人： Joe R. Trogolo ,  Hiroshi Yasuda ,  Badih El-Kareh ,  Philipp Steinmann

    IPC分类号： H01L27/12

    CPC分类号： H01L29/808 ,  H01L29/0607 ,  H01L29/66901

    摘要： The disclosure herein pertains to fashioning an n channel junction field effect transistor (NJFET) and/or a p channel junction field effect transistor (PJFET) with an open drain, where the open drain allows the transistors to operate at higher voltages before experiencing gate leakage current. The open drain allows the voltage to be increased several fold without increasing the size of the transistors. Opening the drain essentially spreads equipotential lines of respective electric fields developed at the drains of the devices so that the local electric fields, and hence the impact ionization rates are reduced to redirect current below the surface of the transistors.

    摘要翻译： 本文的公开内容涉及具有开路漏极的n沟道结场效应晶体管（NJFET）和/或ap沟道结场效应晶体管（PJFET），其中开路漏极允许晶体管在经历栅极漏电流之前以更高的电压工作 。 开路漏极允许电压增加几倍，而不增加晶体管的尺寸。 开放漏极基本上扩散了在器件的漏极处产生的相应电场的等势线，使得局部电场以及因此的冲击电离率被降低以将电流重新导向晶体管表面以下。