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公开(公告)号：US08614486B2
公开(公告)日：2013-12-24
申请号：US13605260
申请日：2012-09-06
CPC分类号： H01L29/66772 , H01L29/6653 , H01L29/78621
摘要： A gate dielectric is patterned after formation of a first gate spacer by anisotropic etch of a conformal dielectric layer to minimize overetching into a semiconductor layer. In one embodiment, selective epitaxy is performed to sequentially form raised epitaxial semiconductor portions, a disposable gate spacer, and raised source and drain regions. The disposable gate spacer is removed and ion implantation is performed into exposed portions of the raised epitaxial semiconductor portions to form source and drain extension regions. In another embodiment, ion implantation for source and drain extension formation is performed through the conformal dielectric layer prior to an anisotropic etch that forms the first gate spacer. The presence of the raised epitaxial semiconductor portions or the conformation dielectric layer prevents complete amorphization of the semiconductor material in the source and drain extension regions, thereby enabling regrowth of crystalline source and drain extension regions.
摘要翻译： 在通过各向异性蚀刻共形介电层形成第一栅极间隔物之后对栅极电介质进行构图，以最小化过蚀刻到半导体层中。 在一个实施例中，执行选择性外延以顺序地形成凸起的外延半导体部分，一次性栅极间隔物和升高的源极和漏极区域。 去除一次性栅极间隔物，并将离子注入进行到隆起的外延半导体部分的暴露部分中以形成源极和漏极延伸区域。 在另一个实施例中，用于源极和漏极延伸形成的离子注入在形成第一栅极间隔物的各向异性蚀刻之前通过保形介电层进行。 升高的外延半导体部分或构象介电层的存在防止了源极和漏极延伸区域中的半导体材料的完全非晶化，从而使结晶源极和漏极延伸区域再生长。
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公开(公告)号：US08486778B2
公开(公告)日：2013-07-16
申请号：US13183666
申请日：2011-07-15
IPC分类号： H01L21/8238 , H01L21/336
CPC分类号： H01L29/66772 , H01L29/6653 , H01L29/78621
摘要： A gate dielectric is patterned after formation of a first gate spacer by anisotropic etch of a conformal dielectric layer to minimize overetching into a semiconductor layer. In one embodiment, selective epitaxy is performed to sequentially form raised epitaxial semiconductor portions, a disposable gate spacer, and raised source and drain regions. The disposable gate spacer is removed and ion implantation is performed into exposed portions of the raised epitaxial semiconductor portions to form source and drain extension regions. In another embodiment, ion implantation for source and drain extension formation is performed through the conformal dielectric layer prior to an anisotropic etch that forms the first gate spacer. The presence of the raised epitaxial semiconductor portions or the conformation dielectric layer prevents complete amorphization of the semiconductor material in the source and drain extension regions, thereby enabling regrowth of crystalline source and drain extension regions.
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公开(公告)号：US20130015512A1
公开(公告)日：2013-01-17
申请号：US13605260
申请日：2012-09-06
IPC分类号： H01L29/78
CPC分类号： H01L29/66772 , H01L29/6653 , H01L29/78621
摘要： A gate dielectric is patterned after formation of a first gate spacer by anisotropic etch of a conformal dielectric layer to minimize overetching into a semiconductor layer. In one embodiment, selective epitaxy is performed to sequentially form raised epitaxial semiconductor portions, a disposable gate spacer, and raised source and drain regions. The disposable gate spacer is removed and ion implantation is performed into exposed portions of the raised epitaxial semiconductor portions to form source and drain extension regions. In another embodiment, ion implantation for source and drain extension formation is performed through the conformal dielectric layer prior to an anisotropic etch that forms the first gate spacer. The presence of the raised epitaxial semiconductor portions or the conformation dielectric layer prevents complete amorphization of the semiconductor material in the source and drain extension regions, thereby enabling regrowth of crystalline source and drain extension regions.
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公开(公告)号：US20130015509A1
公开(公告)日：2013-01-17
申请号：US13183666
申请日：2011-07-15
IPC分类号： H01L29/772 , H01L21/336
CPC分类号： H01L29/66772 , H01L29/6653 , H01L29/78621
摘要： A gate dielectric is patterned after formation of a first gate spacer by anisotropic etch of a conformal dielectric layer to minimize overetching into a semiconductor layer. In one embodiment, selective epitaxy is performed to sequentially form raised epitaxial semiconductor portions, a disposable gate spacer, and raised source and drain regions. The disposable gate spacer is removed and ion implantation is performed into exposed portions of the raised epitaxial semiconductor portions to form source and drain extension regions. In another embodiment, ion implantation for source and drain extension formation is performed through the conformal dielectric layer prior to an anisotropic etch that forms the first gate spacer. The presence of the raised epitaxial semiconductor portions or the conformation dielectric layer prevents complete amorphization of the semiconductor material in the source and drain extension regions, thereby enabling regrowth of crystalline source and drain extension regions.
摘要翻译： 在通过各向异性蚀刻共形介电层形成第一栅极间隔物之后对栅极电介质进行构图，以最小化过蚀刻到半导体层中。 在一个实施例中，执行选择性外延以顺序地形成凸起的外延半导体部分，一次性栅极间隔物和升高的源极和漏极区域。 去除一次性栅极间隔物，并将离子注入进行到隆起的外延半导体部分的暴露部分中以形成源极和漏极延伸区域。 在另一个实施例中，用于源极和漏极延伸形成的离子注入在形成第一栅极间隔物的各向异性蚀刻之前通过保形介电层进行。 升高的外延半导体部分或构象介电层的存在防止了源极和漏极延伸区域中的半导体材料的完全非晶化，从而使结晶源极和漏极延伸区域再生长。
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5.发明授权公开(公告)号：US08394684B2
公开(公告)日：2013-03-12
申请号：US12841408
申请日：2010-07-22
IPC分类号： H01L21/84
CPC分类号： H01L27/0886 , H01L21/82 , H01L29/66795 , H01L29/7847 , H01L29/785
摘要： Techniques are discloses to apply an external stress onto the source/drain semiconductor fin sidewall areas and latch the same onto the semiconductor fin before releasing the sidewalls for subsequent salicidation and contact formation. In particular, the present disclosure provides methods in which selected portions of a semiconductor are subjected to an amorphizing ion implantation which disorients the crystal structure of the selected portions of the semiconductor fins, relative to portions of the semiconductor fin that is beneath a gate stack and encapsulated with various liners. At least one stress liner is formed and then stress memorization occurs by performing a stress latching annealing. During this anneal, recrystallization of the disoriented crystal structure occurs. The at least one stress liner is removed and thereafter merging of the semiconductor fins in the source/drain regions is performed.
摘要翻译： 公开了一种技术来将外部应力施加到源极/漏极半导体鳍状物侧壁区域上并将其锁定到半导体鳍片上，然后释放侧壁以用于随后的盐化和接触形成。 特别地，本公开提供了一种方法，其中半导体的选定部分经受非晶化离子注入，其相对于在栅极堆叠下面的半导体鳍片的部分使半导体鳍片的选定部分的晶体结构脱落， 用各种衬垫封装。 形成至少一个应力衬垫，然后通过进行应力闭锁退火而发生应力记忆。 在该退火期间，发生错位取向的晶体结构的再结晶。 去除至少一个应力衬垫，然后执行源极/漏极区域中的半导体鳍片的合并。
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6.发明申请公开(公告)号：US20120018730A1
公开(公告)日：2012-01-26
申请号：US12841408
申请日：2010-07-22
IPC分类号： H01L29/786 , H01L21/336
CPC分类号： H01L27/0886 , H01L21/82 , H01L29/66795 , H01L29/7847 , H01L29/785
摘要： Techniques are discloses to apply an external stress onto the source/drain semiconductor fin sidewall areas and latch the same onto the semiconductor fin before releasing the sidewalls for subsequent salicidation and contact formation. In particular, the present disclosure provides methods in which selected portions of a semiconductor are subjected to an amorphizing ion implantation which disorients the crystal structure of the selected portions of the semiconductor fins, relative to portions of the semiconductor fin that is beneath a gate stack and encapsulated with various liners. At least one stress liner is formed and then stress memorization occurs by performing a stress latching annealing. During this anneal, recrystallization of the disoriented crystal structure occurs. The at least one stress liner is removed and thereafter merging of the semiconductor fins in the source/drain regions is performed.
摘要翻译： 公开了一种技术来将外部应力施加到源极/漏极半导体鳍状物侧壁区域上并将其锁定到半导体鳍片上，然后释放侧壁以用于随后的盐化和接触形成。 特别地，本公开提供了一种方法，其中半导体的选定部分经受非晶化离子注入，其相对于在栅极堆叠下面的半导体鳍片的部分使半导体鳍片的选定部分的晶体结构脱落， 用各种衬垫封装。 形成至少一个应力衬垫，然后通过进行应力闭锁退火而发生应力记忆。 在该退火期间，发生错位取向晶体结构的重结晶。 去除至少一个应力衬垫，然后执行源极/漏极区域中的半导体鳍片的合并。
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公开(公告)号：US20120326241A1
公开(公告)日：2012-12-27
申请号：US13603572
申请日：2012-09-05
IPC分类号： H01L23/48 , H01L21/768
CPC分类号： H01L21/823807 , H01L21/28518 , H01L21/76805 , H01L21/76829 , H01L21/76895 , H01L21/823814 , H01L21/823871 , H01L23/485 , H01L29/165 , H01L29/41766 , H01L29/665 , H01L29/6659 , H01L29/66636 , H01L29/7834 , H01L29/7843 , H01L29/7848 , H01L2924/0002 , H01L2924/00
摘要： Contact via holes are etched in a dielectric material layer overlying a semiconductor layer to expose the topmost surface of the semiconductor layer. The contact via holes are extended into the semiconductor material layer by continuing to etch the semiconductor layer so that a trench having semiconductor sidewalls is formed in the semiconductor material layer. A metal layer is deposited over the dielectric material layer and the sidewalls and bottom surface of the trench. Upon an anneal at an elevated temperature, a metal semiconductor alloy region is formed, which includes a top metal semiconductor alloy portion that includes a cavity therein and a bottom metal semiconductor alloy portion that underlies the cavity and including a horizontal portion. A metal contact via is formed within the cavity so that the top metal semiconductor alloy portion laterally surrounds a bottom portion of a bottom portion of the metal contact via.
摘要翻译： 在覆盖半导体层的电介质材料层中蚀刻接触孔，以露出半导体层的最上表面。 接触通孔延伸到半导体材料层中，继续蚀刻半导体层，使得在半导体材料层中形成具有半导体侧壁的沟槽。 在电介质材料层和沟槽的侧壁和底表面上沉积金属层。 在高温退火时，形成金属半导体合金区域，其包括顶部金属半导体合金部分，其中包括空腔，底部金属半导体合金部分位于空腔下方并包括水平部分。 金属接触通孔形成在空腔内，使得顶部金属半导体合金部分横向地围绕金属接触通孔的底部的底部。
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公开(公告)号：US20100203717A1
公开(公告)日：2010-08-12
申请号：US12698448
申请日：2010-02-02
IPC分类号： H01L21/28
CPC分类号： H01L29/4238 , H01L21/0337 , H01L21/0338 , H01L21/28123 , H01L21/32139
摘要： A multiple etch process for forming a gate in a semiconductor structure in which a cut area is first formed followed by the forming of the gate conductor lines.
摘要翻译： 在半导体结构中形成栅极的多次蚀刻工艺，其中首先形成切割区域，之后形成栅极导体线。
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公开(公告)号：US08358012B2
公开(公告)日：2013-01-22
申请号：US12849390
申请日：2010-08-03
IPC分类号： H01L29/40
CPC分类号： H01L21/823807 , H01L21/28518 , H01L21/76805 , H01L21/76829 , H01L21/76895 , H01L21/823814 , H01L21/823871 , H01L23/485 , H01L29/165 , H01L29/41766 , H01L29/665 , H01L29/6659 , H01L29/66636 , H01L29/7834 , H01L29/7843 , H01L29/7848 , H01L2924/0002 , H01L2924/00
摘要： Contact via holes are etched in a dielectric material layer overlying a semiconductor layer to expose the topmost surface of the semiconductor layer. The contact via holes are extended into the semiconductor material layer by continuing to etch the semiconductor layer so that a trench having semiconductor sidewalls is formed in the semiconductor material layer. A metal layer is deposited over the dielectric material layer and the sidewalls and bottom surface of the trench. Upon an anneal at an elevated temperature, a metal semiconductor alloy region is formed, which includes a top metal semiconductor alloy portion that includes a cavity therein and a bottom metal semiconductor alloy portion that underlies the cavity and including a horizontal portion. A metal contact via is formed within the cavity so that the top metal semiconductor alloy portion laterally surrounds a bottom portion of a bottom portion of the metal contact via.
摘要翻译： 在覆盖半导体层的电介质材料层中蚀刻接触孔，以露出半导体层的最上表面。 接触通孔延伸到半导体材料层中，继续蚀刻半导体层，使得在半导体材料层中形成具有半导体侧壁的沟槽。 在电介质材料层和沟槽的侧壁和底表面上沉积金属层。 在高温退火时，形成金属半导体合金区域，其包括顶部金属半导体合金部分，其中包括空腔，底部金属半导体合金部分位于空腔下方并包括水平部分。 金属接触通孔形成在空腔内，使得顶部金属半导体合金部分横向地围绕金属接触通孔的底部的底部。
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公开(公告)号：US08377795B2
公开(公告)日：2013-02-19
申请号：US12698448
申请日：2010-02-02
IPC分类号： H01L21/762 , G03C5/00
CPC分类号： H01L29/4238 , H01L21/0337 , H01L21/0338 , H01L21/28123 , H01L21/32139
摘要： A multiple etch process for forming a gate in a semiconductor structure in which a cut area is first formed followed by the forming of the gate conductor lines.
摘要翻译： 在半导体结构中形成栅极的多次蚀刻工艺，其中首先形成切割区域，之后形成栅极导体线。
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