公开(公告)号：US06266353B1

公开(公告)日：2001-07-24

申请号：US09365290

申请日：1999-07-30

申请人： Barry L. Freitas ,  Jay A. Skidmore ,  John P. Wooldridge ,  Mark A. Emanuel ,  Stephen A. Payne

发明人： Barry L. Freitas ,  Jay A. Skidmore ,  John P. Wooldridge ,  Mark A. Emanuel ,  Stephen A. Payne

IPC分类号： H01S5024

CPC分类号： H01S5/02264 ,  H01S5/02252 ,  H01S5/02272 ,  H01S5/02276 ,  H01S5/4018

摘要： A monolithic, electrically-insulating substrate that contains a series of notched grooves is fabricated. The substrate is then metalized so that only the top surface and one wall adjacent to the notch are metalized. Within the grooves is located a laser bar, an electrically-conductive ribbon or contact bar and an elastomer which secures/registers the laser bar and ribbon (or contact bar) firmly along the wall of the groove that is adjacent to the notch. The invention includes several embodiments for providing electrical contact to the corresponding top surface of the adjacent wall. In one embodiment, after the bar is located in the proper position, the electrically conductive ribbon is bent so that it makes electrical contact with the adjoining metalized top side of the heatsink.

摘要翻译： 制造包含一系列凹槽的单片电绝缘基板。 然后将衬底金属化，使得只有顶部表面和与凹口相邻的一个壁被金属化。 在凹槽内设有激光棒，导电带或接触杆和弹性体，其牢固地固定/对准激光棒和带（或接触杆）沿着与凹口相邻的凹槽的壁。 本发明包括用于向相邻壁的对应顶表面提供电接触的若干实施例。 在一个实施例中，在杆位于适当位置之后，导电带被弯曲，使得其与散热器的相邻的金属化顶侧电接触。

公开(公告)号：US4994882A

公开(公告)日：1991-02-19

申请号：US309908

申请日：1989-02-10

申请人： Karl Hess ,  James J. Coleman ,  Ted K. Higman ,  Mark A. Emanuel

发明人： Karl Hess ,  James J. Coleman ,  Ted K. Higman ,  Mark A. Emanuel

IPC分类号： H01L29/76 ,  H01L29/861

CPC分类号： H01L29/7606 ,  H01L29/8618

摘要： A semiconductor heterostructure device is disclosed which includes a first semiconductor layer having a barrier layer disposed thereon, the barrier layer being formed of a semiconductor material having a wider bandgap than the material of the first semiconductor layer. A carrier transport layer is disposed on the barrier layer, the carrier transport layer being formed of a semiconductor material having a narrower bandgap than the material of the barrier layer. A contact layer is disposed on the carrier transport layer. A negative potential is applied to the contact layer with respect to the first semiconductor layer. In operation, for small voltages, under the indicated bias configuration, electrons supplied to the carrier transport layer by the source of negative potential supply will be blocked at the barrier presented by the larger bandgap barrier layer, and little current will flow. As the bias voltage is increased, these blocked electrons are under the influence ofThis invention was made with Government support, and the Government has certain rights in this invention.

摘要翻译： 公开了一种半导体异质结构器件，其包括其上设置有阻挡层的第一半导体层，阻挡层由具有比第一半导体层的材料更宽的带隙的半导体材料形成。 载流子传输层设置在阻挡层上，载流子传输层由具有比阻挡层的材料窄的带隙的半导体材料形成。 接触层设置在载体传输层上。 相对于第一半导体层，对接触层施加负电位。 在操作中，对于小电压，在指定的偏压构造下，由负电位源供应到载流子传输层的电子将在由较大带隙势垒层呈现的屏障处被阻挡，并且很少的电流将流过。 随着偏置电压的增加，这些被阻塞的电子受到增加的电场的影响，这提高了电子能量。 在某些时候，这些“加热”电子将突然具有足够的能量穿过势垒并有助于较大的电流。 在这两种类型的电流之间可能发生转换，结果是S型电流 - 电压特性，可用于获得非常快的双态器件。

公开(公告)号：US07189589B2

公开(公告)日：2007-03-13

申请号：US10735695

申请日：2003-12-16

申请人： Glen Phillip Carey ,  Ian Jenks ,  Alan Lewis ,  René Lujan ,  Hailong Zhou ,  Jacy R. Titus ,  Gideon W. Yoffe ,  Mark A. Emanuel ,  Aram Mooradian

发明人： Glen Phillip Carey ,  Ian Jenks ,  Alan Lewis ,  René Lujan ,  Hailong Zhou ,  Jacy R. Titus ,  Gideon W. Yoffe ,  Mark A. Emanuel ,  Aram Mooradian

IPC分类号： H01L21/00

CPC分类号： H01S5/18305 ,  H01L21/02395 ,  H01L21/02543 ,  H01L21/02546 ,  H01L33/0079 ,  H01S5/0217 ,  H01S5/0224 ,  H01S5/141 ,  H01S5/323

摘要： A method of fabricating a semiconductor device is described. In this method, a starting substrate of sufficient thickness is selected that has the required defect density levels, which may result in an undesirable doping level. Then a semiconductor layer having a desired doping level is formed on the starting substrate. The resulting semiconductor layer has the required defect density and doping levels for the final product application. After active components, electrical conductors, and any other needed structures are formed on the semiconductor layer, the starting substrate is removed leaving a desired thickness of the semiconductor layer. In a VECSEL application, the active components can be a gain cavity, where the semiconductor layer has the necessary defect density and doping levels to maximize wall plug efficiency (WPE). In one embodiment, the doping of the semiconductor layer is not uniform. For example, a majority of the layer is doped at a low level and the remainder is doped at a much higher level. This can result in improved WPE at particular thicknesses for the higher doped material.

摘要翻译： 描述制造半导体器件的方法。 在该方法中，选择具有所需缺陷密度水平的足够厚度的起始衬底，这可能导致不期望的掺杂水平。 然后在起始衬底上形成具有期望的掺杂水平的半导体层。 所得到的半导体层具有所需的缺陷密度和最终产品应用的掺杂水平。 在有源部件之后，在半导体层上形成电导体和任何其它需要的结构，去除起始衬底，留出半导体层的所需厚度。 在VECSEL应用中，有源部件可以是增益腔，其中半导体层具有必要的缺陷密度和掺杂水平以最大化壁插拔效率（WPE）。 在一个实施例中，半导体层的掺杂不均匀。 例如，该层的大部分以低电平掺杂，其余部分以高得多的水平掺杂。 这可以导致用于较高掺杂材料的特定厚度的改进的WPE。