摘要:
An apparatus for pre-processing of a digital video data stream including luminance and chrominance pixel data, the apparatus comprising a plurality of pre-processing units including a horizontal filter unit and a vertical filter unit. The horizontal filter unit is located at an input side and the vertical filter unit is located at an output side of the preprocessing apparatus and wherein all read/write memory for storing data outputted from or inputted to the plurality of pre-processing units is contained in a single memory block.
摘要:
The invention relates to an error-correction method for use in a process of decoding cross-interleaved Reed-Solomon code (CIRC) that corrects errors in data stored as C1 code words and C2 code words in a memory with several locations, each of said locations containing a data byte of said data, and an apparatus performing said method. The new method implies specific regulations for defining which data words are to be used for C1 and C2 decoding and for the processing order. The system memory for a deinterleaver implementation can be of a smaller size as compared to conventional memories. In addition, only a single CIRC decoder needs to be used for performing the process of decoding cross-interleaved Reed-Solomon code.
摘要:
A method and apparatus for preventing unauthorized use of DVDs on a DVD ROM drive. The method comprises a DVD disc that includes special data processing. When the DVD is replayed on a standard DVD ROM drive the invention causes the output of the DVD ROM drive to be erroneous, such that the computer cannot use the data. According to the invention, when encoding a disc, the error correction and/or error detection bits, check bytes, are moved into the normal or main data area. When this scrambled data is output from a standard DVD ROM drive, the data in the check byte area is lost and the information is not useable. For authorized use, this scrambling is reversed before sending video and/or audio data to the MPED decoder and AC-3 decoder respectively.
摘要:
A digital detector circuit for recovering the bit timing of a data stream with a PLL includes a digital phase detector and a digital pulse length detector whose output signals are added and integrated, and the result is used for controlling the oscillator frequency. The output signal of the pulse length detector is determined by a corresponding algorithm, one slow and two fast, with direction-dependent output signals of the pulse length detector being generated.