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    Regulated power supply with multiple regulators sharing the total current supplied to a load
    1.
    发明申请
    Regulated power supply with multiple regulators sharing the total current supplied to a load 有权
    具有多个调节器的稳压电源共享供给负载的总电流

    公开(公告)号：US20070200538A1

    公开(公告)日：2007-08-30

    申请号：US11364750

    申请日：2006-02-28

    申请人： Benjamin Tang ,  Scott Southwell ,  Kenneth Ostrom

    发明人： Benjamin Tang ,  Scott Southwell ,  Kenneth Ostrom

    IPC分类号： G05F1/00

    CPC分类号： H02M3/158 ,  H02M3/157 ,  H02M3/1584 ,  Y10T307/565

    摘要： Disclosed is a digital current sharing structure and method in which a plurality of regulators are configured to share the load current. Current share circuits in each of the regulators are configured to measure and compare the average current provided by that particular regulator with the overall average current provided by all the regulators. Each of the current share circuits then provides an output so that the output of each regulator is adjusted to provide the same amount of current to the load. Digital processing with both analog and digital averaging are disclosed. Also disclosed is a programmable hysteresis technique to eliminate relatively trivial adjustments.

    摘要翻译： 公开了一种数字电流共享结构和方法，其中多个稳压器被配置为共享负载电流。 每个稳压器中的电流共享电路配置为测量和比较由该特定稳压器提供的平均电流与所有稳压器提供的总体平均电流。 然后，每个当前共享电路提供输出，使得每个调节器的输出被调整以向负载提供相同量的电流。 公开了具有模拟和数字平均的数字处理。 还公开了一种用于消除相对微不足道的调整的可编程滞后技术。

    Active transient response circuits, system and method for digital multiphase pulse width modulated regulators
    2.
    发明申请
    Active transient response circuits, system and method for digital multiphase pulse width modulated regulators 有权

    公开(公告)号：US20060152205A1

    公开(公告)日：2006-07-13

    申请号：US11311115

    申请日：2005-12-19

    申请人： Benjamim Tang ,  Robert Carroll ,  Scott Southwell ,  Kenneth Ostrom ,  Richard Pierson

    发明人： Benjamim Tang ,  Robert Carroll ,  Scott Southwell ,  Kenneth Ostrom ,  Richard Pierson

    IPC分类号： G05F1/40 ,  G05F1/56

    CPC分类号： H02M3/1584

    摘要： Disclosed is a multi-phase pulse width modulated voltage regulator and method in which transient voltage excursions or deviations that exceed the load line voltage by more than a pre-determined amount are detected by an ATR circuit and a correction signal is applied. The correction signal is in the form of asynchronous pulses and the number of such pulses is a function of the magnitude of the voltage excursion as determined by the number of thresholds that are exceeded. Also disclosed is an adaptive voltage positioning (AVP) circuit and method for early detection of a transient event by sensing voltage changes at the load and adjusting the target voltage with pre-determined current values prior to the time that ATR event changes in the current at the load are detected. The AVP load line is pre-positioned for more precise current control. Also disclosed is an adaptive filter with adjustable frequency characteristics in response to an ATR event. Also disclosed is a pulse limiting circuit. Also disclosed is a tri-state implementation. Response to transient events is further improved with an external ATR circuit coupled to the load.

    PLL/DLL dual loop data synchronization utilizing a granular FIFO fill level indicator
    3.
    发明授权
    PLL/DLL dual loop data synchronization utilizing a granular FIFO fill level indicator 有权
    PLL / DLL双循环数据同步利用粒度FIFO填充水平指示器

    公开(公告)号：US07366270B2

    公开(公告)日：2008-04-29

    申请号：US10029709

    申请日：2001-12-20

    申请人： Benjamin Tang ,  Scott Southwell ,  Nicholas Robert Steffen

    发明人： Benjamin Tang ,  Scott Southwell ,  Nicholas Robert Steffen

    IPC分类号： H04L7/00 ,  H03D3/24 ,  H03L7/00

    CPC分类号： G06F5/12 ,  G06F2205/061 ,  H03L7/081 ,  H03L7/087 ,  H04J3/047 ,  H04J3/062 ,  H04J3/0685

    摘要： A dual loop (PLL/DLL) data synchronization system and method for plesiochronous systems is provided. In particular, a system and method for dual loop data synchronization using a granular FIFO fill level indicator is provided. A dual loop data serializer includes a phase lock loop (PLL) and a delayed lock loop (DLL) configured with a phase shifter in the feedback path of the PLL. The dual loop serializer locks to the input of the DLL, which represents a fill level of a FIFO. A granular FIFO fill level indicator of the DLL provides input to the phase shifter to adjust the frequency of the PLL accordingly. Thus, the frequency of the data input rate can be controlled and a constant fill level of the FIFO can be maintained. A dual loop retimer includes a dual loop serializer (PLL/DLL) and a clock recovery DLL. The retimer resets the jitter budget to meet transmission requirements for an infinite number of repeater stages.

    摘要翻译： 提供了一种双循环（PLL / DLL）数据同步系统和方法，用于同步系统。 特别地，提供了一种使用粒度FIFO填充水平指示符的双循环数据同步的系统和方法。 双环数据串行器包括在PLL的反馈路径中配置有移相器的锁相环（PLL）和延迟锁环（DLL）。 双循环串行器锁定到DLL的输入，它表示FIFO的填充级别。 该DLL的粒状FIFO填充电平指示器为移相器提供输入以相应地调整PLL的频率。 因此，可以控制数据输入速率的频率，并且可以保持FIFO的恒定填充电平。 双环重定时器包括双回路串行器（PLL / DLL）和时钟恢复DLL。 重新定时器重置抖动预算以满足无限数量的中继器级的传输要求。

    Multi-threshold multi-gain active transient response circuit and method for digital multiphase pulse width modulated regulators
    4.
    发明申请
    Multi-threshold multi-gain active transient response circuit and method for digital multiphase pulse width modulated regulators 有权

    公开(公告)号：US20060055388A1

    公开(公告)日：2006-03-16

    申请号：US10938031

    申请日：2004-09-10

    申请人： Benjamin Tang ,  Robert Carroll ,  Scott Southwell

    发明人： Benjamin Tang ,  Robert Carroll ,  Scott Southwell

    IPC分类号： G05F1/40

    CPC分类号： H02M3/1584

    摘要： Disclosed is a multi-phase pulse width modulated voltage regulator and method in which transient voltage excursions or deviations that exceed the load line voltage by more than a pre-determined amount are detected by an ATR circuit and a correction signal is applied. The correction signal is in the form of asynchronous pulses and the number of such pulses is a function of the magnitude of the voltage excursion as determined by the number of thresholds that are exceeded. Also disclosed is an adaptive voltage positioning (AVP) circuit and method for early detection of a transient event by sensing voltage changes at the load and adjusting the target voltage with pre-determined current values prior to the time that ATR event changes in the current at the load are detected.

    PLL/DLL dual loop data synchronization
    5.
    发明授权
    PLL/DLL dual loop data synchronization 有权
    PLL / DLL双循环数据同步

    公开(公告)号：US08239579B2

    公开(公告)日：2012-08-07

    申请号：US12719450

    申请日：2010-03-08

    申请人： Benjamim Tang ,  Scott Southwell ,  Nicholas Robert Steffen

    发明人： Benjamim Tang ,  Scott Southwell ,  Nicholas Robert Steffen

    IPC分类号： G06F15/16

    CPC分类号： H04J3/047 ,  H04J3/062 ,  H04J3/0685 ,  H04L7/033

    摘要： A dual loop (PLL/DLL) data synchronization system and method for plesiochronous systems is provided. A dual loop data serializer includes a phase lock loop (PLL) and a delayed lock loop (DLL) configured with a phase shifter in the feedback path of the PLL. The dual loop serializer locks to the input of the DLL instead of the local reference. Thus, the DLL adjusts the frequency from the PLL so that it matches the desired data rate. Each loop may be optimized for jitter tolerance with the net effect generating a synthesized clean clock (due to narrow bandwidth filtering) and VCO noise suppression (due to wide bandwidth filtering). A dual loop retimer includes a dual loop serializer (PLL/DLL) and a clock recovery DLL. The retimer resets the jitter budget to meet transmission requirements for an infinite number of repeater stages.

    摘要翻译： 提供了一种双循环（PLL / DLL）数据同步系统和方法，用于同步系统。 双环数据串行器包括在PLL的反馈路径中配置有移相器的锁相环（PLL）和延迟锁环（DLL）。 双循环串行器锁定到DLL的输入，而不是本地引用。 因此，DLL调整来自PLL的频率，使其与期望的数据速率相匹配。 每个环路可以针对抖动容限进行优化，其净效应产生合成的干净时钟（由于窄带宽滤波）和VCO噪声抑制（由于宽带宽滤波）。 双环重定时器包括双回路串行器（PLL / DLL）和时钟恢复DLL。 重新定时器重置抖动预算以满足无限数量的中继器级的传输要求。

    PLL/DLL dual loop data synchronization
    6.
    发明授权
    PLL/DLL dual loop data synchronization 有权
    PLL / DLL双循环数据同步

    公开(公告)号：US07743168B2

    公开(公告)日：2010-06-22

    申请号：US12077002

    申请日：2008-03-14

    申请人： Benjamim Tang ,  Scott Southwell ,  Nicholas Robert Steffen

    发明人： Benjamim Tang ,  Scott Southwell ,  Nicholas Robert Steffen

    IPC分类号： G06F15/16

    CPC分类号： H04J3/047 ,  H04J3/062 ,  H04J3/0685 ,  H04L7/033

    摘要： A dual loop (PLL/DLL) data synchronization system and method for plesiochronous systems is provided. A dual loop data serializer includes a phase lock loop (PLL) and a delayed lock loop (DLL) configured with a phase shifter in the feedback path of the PLL. The dual loop serializer locks to the input of the DLL instead of the local reference. Thus, the DLL adjusts the frequency from the PLL so that it matches the desired data rate. Each loop may be optimized for jitter tolerance with the net effect generating a synthesized clean clock (due to narrow bandwidth filtering) and VCO noise suppression (due to wide bandwidth filtering). A dual loop retimer includes a dual loop serializer (PLL/DLL) and a clock recovery DLL. The retimer resets the jitter budget to meet transmission requirements for an infinite number of repeater stages.

    摘要翻译： 提供了一种双循环（PLL / DLL）数据同步系统和方法，用于同步系统。 双环数据串行器包括在PLL的反馈路径中配置有移相器的锁相环（PLL）和延迟锁环（DLL）。 双循环串行器锁定到DLL的输入，而不是本地引用。 因此，DLL调整来自PLL的频率，使其与期望的数据速率相匹配。 每个环路可以针对抖动容限进行优化，其净效应产生合成的干净时钟（由于窄带宽滤波）和VCO噪声抑制（由于宽带宽滤波）。 双环重定时器包括双回路串行器（PLL / DLL）和时钟恢复DLL。 重新定时器重置抖动预算以满足无限数量的中继器级的传输要求。

    PLL/DLL dual loop data synchronization
    8.
    发明申请
    PLL/DLL dual loop data synchronization 有权
    PLL / DLL双循环数据同步

    公开(公告)号：US20080212730A1

    公开(公告)日：2008-09-04

    申请号：US12077002

    申请日：2008-03-14

    申请人： Benjamim Tang ,  Scott Southwell ,  Nicholas Steffen

    发明人： Benjamim Tang ,  Scott Southwell ,  Nicholas Steffen

    IPC分类号： H03D3/24

    CPC分类号： H04J3/047 ,  H04J3/062 ,  H04J3/0685 ,  H04L7/033

    摘要： A dual loop (PLL/DLL) data synchronization system and method for plesiochronous systems is provided. A dual loop data serializer includes a phase lock loop (PLL) and a delayed lock loop (DLL) configured with a phase shifter in the feedback path of the PLL. The dual loop serializer locks to the input of the DLL instead of the local reference. Thus, the DLL adjusts the frequency from the PLL so that it matches the desired data rate. Each loop may be optimized for jitter tolerance with the net effect generating a synthesized clean clock (due to narrow bandwidth filtering) and VCO noise suppression (due to wide bandwidth filtering). A dual loop retimer includes a dual loop serializer (PLL/DLL) and a clock recovery DLL. The retimer resets the jitter budget to meet transmission requirements for an infinite number of repeater stages.

    摘要翻译： 提供了一种双循环（PLL / DLL）数据同步系统和方法，用于同步系统。 双环数据串行器包括在PLL的反馈路径中配置有移相器的锁相环（PLL）和延迟锁环（DLL）。 双循环串行器锁定到DLL的输入，而不是本地引用。 因此，DLL调整来自PLL的频率，使其与期望的数据速率相匹配。 每个环路可以针对抖动容限进行优化，其净效应产生合成的干净时钟（由于窄带宽滤波）和VCO噪声抑制（由于宽带宽滤波）。 双环重定时器包括双回路串行器（PLL / DLL）和时钟恢复DLL。 重新定时器重置抖动预算以满足无限数量的中继器级的传输要求。

    Digital Calibration with Lossless Current Sensing in a Multiphase Switched Power Converter
    9.
    发明申请
    Digital Calibration with Lossless Current Sensing in a Multiphase Switched Power Converter 有权
    数字校准与多相开关电源转换器中的无损耗电流检测

    公开(公告)号：US20070257650A1

    公开(公告)日：2007-11-08

    申请号：US11779487

    申请日：2007-07-18

    申请人： Scott Southwell ,  Benjamim Tang ,  Robert Carroll ,  Steven Schulte

    发明人： Scott Southwell ,  Benjamim Tang ,  Robert Carroll ,  Steven Schulte

    IPC分类号： G05F1/00

    CPC分类号： H02M3/1584 ,  H02M2001/0009

    摘要： Disclosed is a multi-phase power regulator that accurately senses current at a load in a lossless manner and adjusts the power supplied to the load based on the sensed current. Also disclosed is a method of calibrating a multiphase voltage regulator by applying a known calibration current at the load and determining actual current values by the difference in measured values between when the known calibration current is applied and when it is not applied. The accurate current is determined at a known temperature and accurate temperature compensation is provided by a non-linear digital technique. Each phase of the multi-phase power regulator is individually calibrated so that balanced channels provide accurate power to the load. Also disclosed is a calibration method with minimal noise generation.

    摘要翻译： 公开了一种多相功率调节器，其以无损耗的方式精确地感测负载处的电流，并且基于感测的电流来调节提供给负载的功率。 还公开了一种通过在负载处施加已知的校准电流来校准多相电压调节器的方法，并且通过施加已知的校准电流与不施加之间的测量值之间的差来确定实际电流值。 在已知温度下确定精确电流，并通过非线性数字技术提供精确的温度补偿。 单相校准多相功率调节器的每相，以便平衡通道为负载提供精确的功率。 还公开了一种具有最小噪声产生的校准方法。