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    Switching Regulator Output Capacitor Current Estimation
    1.
    发明申请
    Switching Regulator Output Capacitor Current Estimation 有权
    开关稳压器输出电容电流估计

    公开(公告)号：US20140002044A1

    公开(公告)日：2014-01-02

    申请号：US13537856

    申请日：2012-06-29

    Applicant: Amir Babazadeh ,  Benjamim Tang ,  Kenneth Ostrom

    Inventor： Amir Babazadeh ,  Benjamim Tang ,  Kenneth Ostrom

    IPC: G05F1/10

    CPC classification number: H02M3/1588 ,  H02M3/1584 ,  H02M2001/0009 ,  Y02B70/1466

    Abstract: A switching regulator includes a controller and a power stage for coupling to a load through an inductor and a capacitor. The a controller is operable to control operation of the power stage via a pulse width modulation (PWM) signal generated based on a difference between a reference voltage and the load voltage and sample the inductor current at a lower rate than the load voltage. The controller is further operable to estimate the capacitor current based on the sampled load voltage, generate an offset to the reference voltage based on the sampled inductor current and the estimated capacitor current and adjust the PWM signal applied to the power stage based on the offset. The switching regulator can be single-phase or multi-phase.

    Abstract translation: 开关调节器包括控制器和用于通过电感器和电容器耦合到负载的功率级。 控制器可操作以经由基于参考电压和负载电压之间的差产生的脉冲宽度调制（PWM）信号来控制功率级的操作，并以比负载电压更低的速率对电感器电流进行采样。 控制器进一步可操作以基于采样的负载电压来估计电容器电流，基于采样的电感器电流和估计的电容器电流产生对参考电压的偏移，并且基于偏移来调整施加到功率级的PWM信号。 开关稳压器可以是单相或多相。

    METHODS AND APPARATUS FOR POWER SUPPLY LOAD DUMP COMPENSATION
    3.
    发明申请
    METHODS AND APPARATUS FOR POWER SUPPLY LOAD DUMP COMPENSATION 有权
    电源负载补偿的方法和装置

    公开(公告)号：US20100013452A1

    公开(公告)日：2010-01-21

    申请号：US12505838

    申请日：2009-07-20

    Applicant: BENJAMIM TANG ,  Timothy M. Ng

    Inventor： BENJAMIM TANG ,  Timothy M. Ng

    IPC: G05F1/10

    CPC classification number: H02M3/156 ,  H02M2001/0019 ,  H03K7/08 ,  Y10S323/901

    Abstract: Methods and apparatus for power supply load dump compensation according to various aspects of the present invention may operate in conjunction with a power stage system, such as a power stage system comprising a bootstrapped driver circuit and a power stage responsive to the driver circuit. The power stage system may further include a load dump compensation circuit connected to the driver circuit, wherein the load dump compensation circuit is configured to remove a bias current generated by the bootstrapped driver circuit. Various aspects of the present invention may be implemented in conjunction with any appropriate power supply, such as a switching regulator, for example a buck converter.

    Abstract translation: 根据本发明的各个方面的用于电源负载突降补偿的方法和装置可以与功率级系统结合操作，功率级系统例如包括自举驱动电路和响应于驱动器电路的功率级的功率级系统。 功率级系统还可以包括连接到驱动器电路的负载突降补偿电路，其中负载突降补偿电路被配置为去除由自举驱动电路产生的偏置电流。 本发明的各个方面可以结合任何适当的电源，例如开关调节器，例如降压转换器来实现。

    Cross-point switch fabric and switch fabric slice
    4.
    发明授权
    Cross-point switch fabric and switch fabric slice 有权
    交叉矩阵交换矩阵和交换矩阵

    公开(公告)号：US07385969B2

    公开(公告)日：2008-06-10

    申请号：US10278501

    申请日：2002-10-23

    Applicant: Benjamim Tang ,  Keith N. Bassett

    Inventor： Benjamim Tang ,  Keith N. Bassett

    IPC: H04Q11/00

    CPC classification number: H04Q3/68 ,  H04Q2213/13003 ,  H04Q2213/1302 ,  H04Q2213/1304 ,  H04Q2213/13103 ,  H04Q2213/1334

    Abstract: A cross-point switch fabric slice (100) includes multistage gated buffer tree (135) incorporating at least first and second serially connected gated buffer stages (136, 138). N inputs (102-116) connect to preselected gated buffers (146-160) in the first gated buffer stage (136). The multistage gated buffer tree provides a signal path from any of the N inputs (102-116) to at least one switch output (118) in response to gated buffer stage control signals for the first gated buffer stage (136) and gated buffer stage control signals for the second gated buffer stage (138). Generally, the number of gated buffers decreases from that of the previous stage. As an input signal propagates through the cross-point switch fabric slice (100), longer internal connections are driven by more capable buffers.

    Abstract translation: 交叉点交换结构切片（100）包括结合至少第一和第二串联连接的门控缓冲级（136,138）的多阶门控缓冲器树（135）。 在第一门控缓冲级（136）中，N个输入（102-116）连接到预先选通的门控缓冲器（146-160）。 响应于第一门控缓冲级（136）和门控缓冲级（136）的门控缓冲级控制信号，多级门控缓冲器树提供从N个输入（102-116）中的任何一个到至少一个开关输出（118）的信号路径 用于第二门控缓冲级（138）的控制信号。 通常，门控缓冲器的数量从前一阶段的数量减少。 当输入信号通过交叉点开关织物切片（100）传播时，较长的内部连接由更有能力的缓冲器驱动。

    Multiphase power regulator with load adaptive phase control
    5.
    发明申请
    Multiphase power regulator with load adaptive phase control 有权
    具有负载自适应相位控制功能的多相电源调节器

    公开(公告)号：US20070013350A1

    公开(公告)日：2007-01-18

    申请号：US11480715

    申请日：2006-07-03

    Applicant: Benjamim Tang ,  Robert Carroll ,  Nicholas Steffen ,  Richard Pierson

    Inventor： Benjamim Tang ,  Robert Carroll ,  Nicholas Steffen ,  Richard Pierson

    IPC: G05F1/00

    CPC classification number: H02M3/1584 ,  H02M2001/0009 ,  H02M2001/0012

    Abstract: Disclosed is a power regulator for providing precisely regulated power to a microelectronic device such as a microprocessor. Improved power regulation is accomplished by optimizing the power efficiency of the power regulator. In particular, in a multiphase system, the number of active phases is increased or decreased to achieve optimum power efficiency. The multiphase voltage regulator adapts the operating mode to maximize efficiency as the load current demand of the load device changes by adjusting the number of active phases to maximize efficiency. The total value of current provided by the regulator and the total number of active phases is determined, the total number of active phases is compared with the number of active phases required to provide the total value of current at maximum efficiency; and the number of active phases is adjusted to provide the total value of current at maximum efficiency. A current sense circuit senses the current at each phase, a summing circuit coupled to the output of the current sense circuit provides the total current value of all the measured phases, a circuit coupled to the output of the summing circuit provides the time averaged total current value to a threshold detecting circuit that determines the number of phases at which the voltage regulator should be operating for maximum efficiency, and a circuit for comparing the number of phases that are operating to the number of phases at which the voltage regulator should be operating adjusts the number of active phases to the number of phases at which the voltage regulator should be operating for maximum efficiency.

    Abstract translation: 公开了一种功率调节器，用于向诸如微处理器的微电子器件提供精确调节的功率。 通过优化功率调节器的功率效率来实现改进的功率调节。 特别地，在多相系统中，活性相的数量增加或减少以达到最佳功率效率。 当负载设备的负载电流需求通过调节活动相数量来最大化效率而改变时，多相电压调节器可以适应操作模式以最大化效率。 确定调节器提供的电流总值和有效相的总数，将有效相的总数与最大效率提供电流总值所需的有效相数进行比较; 并且调整活动相的数量以提供最大效率的电流总值。 电流感测电路感测每相的电流，耦合到电流检测电路的输出的求和电路提供所有测量相位的总电流值，耦合到求和电路的输出的电路提供时间平均总电流 值到阈值检测电路，其确定电压调节器应该在最大效率下操作的相位数，以及用于将正在操作的相位数与用于调节电压的相位数进行比较的电路进行调整 电压调节器应运行的相数达到最大效率的有效相数。

    Dual loop regulator
    7.
    发明授权
    Dual loop regulator 有权
    双回路调节器

    公开(公告)号：US06809504B2

    公开(公告)日：2004-10-26

    申请号：US10104199

    申请日：2002-03-21

    Applicant: Benjamim Tang ,  Ken Ostrom ,  Tim Ng ,  Clifford Duong

    Inventor： Benjamim Tang ,  Ken Ostrom ,  Tim Ng ,  Clifford Duong

    IPC: G05F156

    CPC classification number: G06F1/305 ,  G06F1/26

    Abstract: A dual loop regulator is configured for improved regulation of a supply voltage for a dynamic load based on the magnitude of changes in the load voltage. An exemplary dual loop regulator comprises a primary voltage regulator configured within a linear loop and a secondary voltage regulator configured within a wideband, non-linear loop. The primary voltage regulator is configured for providing a well-controlled, regulated output voltage to the dynamic load, and for addressing small changes in the output voltage. The secondary voltage regulator is configured for sensing undervoltage and overvoltage conditions at the dynamic load, and for addressing changes greater than a predetermined threshold voltage. To facilitate loop stability, secondary voltage regulator can be configured within the wideband, non-linear loop to have a small gain for small changes, a larger gain for large changes, and/or a substantially finite storage capability such that any large signal oscillations will not be sustained.

    Abstract translation: 双回路调节器被配置为基于负载电压变化的幅度改进对动态负载的电源电压的调节。 示例性双回路调节器包括配置在线性环路内的初级电压调节器和配置在宽带非线性环路内的次级电压调节器。 主电压调节器配置为向动态负载提供良好控制的稳压输出电压，并用于解决输出电压的小变化。 次级电压调节器被配置用于在动态负载下感测欠压和过压状态，以及用于寻址大于预定阈值电压的变化。 为了方便环路稳定性，可以在宽带非线性环路内配置二次电压调节器，以实现小变化的小增益，大变化的较大增益和/或基本有限的存储能力，使得任何大的信号振荡将 不能持续

    Method and circuit for pre-emphasis equalization in high speed data communications
    8.
    发明授权
    Method and circuit for pre-emphasis equalization in high speed data communications 有权

    公开(公告)号：US06570406B2

    公开(公告)日：2003-05-27

    申请号：US10010825

    申请日：2001-11-13

    Applicant: Benjamim Tang ,  Richard C. Pierson

    Inventor： Benjamim Tang ,  Richard C. Pierson

    IPC: H03K19003

    CPC classification number: H04L25/0286 ,  H04L25/0272 ,  H04L25/0288 ,  H04L25/03878

    Abstract: A method and circuit for pre-emphasis equalization of a high speed data communication system can be provided through the use of programmable pulse shaping. A data communication system configured with the pre-emphasis equalization circuit operates by receiving an input data stream and outputting a data stream for transmission through an interconnect or other transmission channel. The data can be passed through an output buffer configured with programmable pre-emphasis equalization, having input inverters at an input stage and output inverters at an output stage. During operation, once an input signal to the input stage transitions, for example from a low to a high state, an input signal to the output stage is configured to a full amplitude to drive the transmission channel. Once the output stage transitions to a full amplitude, the input of the output stage is configured closer to a mid-scale amplitude. The amount of amplitude change from full scale back to mid-scale determines the amount of equalization to be provided by the output buffer to the transmission channel.

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