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1.发明授权System and method for providing improved bus utilization via target directed completion 失效通过目标定向完成提供改进的总线利用率的系统和方法公开(公告)号：US06973520B2
公开(公告)日：2005-12-06
申请号：US10195172
申请日：2002-07-11
申请人： Bernard Charles Drerup , Jaya Prakash Subramaniam Ganasan , Richard Gerard Hofmann , Richard Nicholas Iachetta, Jr. , Barry Joe Wolford
发明人： Bernard Charles Drerup , Jaya Prakash Subramaniam Ganasan , Richard Gerard Hofmann , Richard Nicholas Iachetta, Jr. , Barry Joe Wolford
IPC分类号： G06F13/00 , G06F13/14 , G06F13/364
CPC分类号： G06F13/364
摘要： An electronic system is disclosed, including multiple initiators and one or more targets coupled to a bus, and a request mask control unit (RMCU). The initiators are configured to initiate requests (e.g., read requests and write requests) via the bus, and the targets are configured to receive requests from the initiators via the bus. The targets are also configured to produce multiple MaskEnable signals, wherein each of the MaskEnable signals is generated following an initial request received via the bus, and dependent on a corresponding “masking situation” within the target. The RMCU receives the MaskEnable signals and produces multiple RequestMask signals dependent upon the MaskEnable signals. One or more of the initiators are permitted to repeat requests via the bus dependent upon one or more of the RequestMask signals. This mechanism provides additional bus bandwidth for carrying out successful data transfers.
摘要翻译： 公开了一种电子系统，包括多个启动器和耦合到总线的一个或多个目标，以及请求掩码控制单元（RMCU）。 启动器被配置为经由总线发起请求（例如，读请求和写请求），并且目标被配置为经由总线接收来自发起者的请求。 目标还被配置为产生多个MaskEnable信号，其中每个MaskEnable信号是在经由总线接收到的初始请求之后生成的，并且取决于目标内相应的“屏蔽情况”。 RMCU接收MaskEnable信号，并根据MaskEnable信号产生多个RequestMask信号。 一个或多个启动器被允许经由总线重复请求，取决于一个或多个请求掩码信号。 该机制为进行成功的数据传输提供了额外的总线带宽。
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2.发明授权Method and apparatus for passing messages through a bus-to-bus bridge while maintaining ordering 失效用于在保持排序的同时通过总线到总线桥接信息的方法和装置公开(公告)号：US06801977B2
公开(公告)日：2004-10-05
申请号：US10042096
申请日：2002-01-07
IPC分类号： G07F1336
CPC分类号： G06F13/4059
摘要： An apparatus and method for passing messages through a bus-to-bus bridge while maintaining ordering. The method comprises passing messages into a message container in the bus bridge without using the bridge buffer, setting a flag that tracks all the writes in the write queue ahead of when the message was put into the message container, blocking the receiving device on the bus connected to the bridge from accessing the message container until the flag is cleared, and clearing the flag when all the writes put into the write queue ahead of when the flag was set have been written to local memory on the receiving bus, then allowing the device on the receiving bus that is the intended recipient to receive the message.
摘要翻译： 一种用于在保持排序的同时通过总线到总线桥接信息的装置和方法。 该方法包括将消息传递到总线桥中的消息容器中，而不使用桥接缓冲器，设置在消息被放入消息容器之前跟踪写入队列中的所有写入的标志，阻止总线上的接收设备 连接到桥接器访问消息容器直到标志被清除，并且当在设置标志之后写入队列的所有写入已经被写入到接收总线上的本地存储器中时清除标志，然后允许该设备 在接收消息的接收总线上。
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3.发明授权Structure for maintaining memory data integrity in a processor integrated circuit using cache coherency protocols 有权使用高速缓存一致性协议在处理器集成电路中维护存储器数据完整性的结构公开(公告)号：US08266386B2
公开(公告)日：2012-09-11
申请号：US12277297
申请日：2008-11-25
CPC分类号： G06F12/0817 , G06F17/5022
摘要： A design structure for a processor system may be embodied in a machine readable medium for designing, manufacturing or testing a processor integrated circuit. The design structure may embody a processor integrated circuit including multiple processors with respective processor cache memories. The design structure may specify enhanced cache coherency protocols to achieve cache memory integrity in a multi-processor environment. The design structure may describe a processor bus controller manages cache coherency bus interfaces to master devices and slave devices. The design structure may also describe a master I/O device controller and a slave I/O device controller that couple directly to the processor bus controller while system memory couples to the processor bus controller via a memory controller. In one embodiment, the design structure may specify that the processor bus controller blocks partial responses that it receives from all devices except the slave I/O device from being included in a combined response that the processor bus controller sends over the cache coherency buses.
摘要翻译： 用于处理器系统的设计结构可以体现在用于设计，制造或测试处理器集成电路的机器可读介质中。 该设计结构可以包括具有相应处理器高速缓冲存储器的包括多个处理器的处理器集成电路。 设计结构可以指定增强的高速缓存一致性协议以在多处理器环境中实现高速缓存存储器完整性。 设计结构可以描述处理器总线控制器管理高速缓存一致性总线接口到主设备和从设备。 该设计结构还可以描述主系统存储器通过存储器控制器耦合到处理器总线控制器的主I / O设备控制器和从属I / O设备控制器，其直接耦合到处理器总线控制器。 在一个实施例中，设计结构可以指定处理器总线控制器阻止从除了从I / O设备之外的所有设备接收的部分响应被包括在处理器总线控制器通过高速缓存一致性总线发送的组合响应中。
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4.发明申请Cache Intervention on a Separate Data Bus When On-Chip Bus Has Separate Read and Write Data Busses 有权当片上总线具有独立的读写数据总线时，在单独数据总线上进行缓存干预公开(公告)号：US20090177821A1
公开(公告)日：2009-07-09
申请号：US11969256
申请日：2008-01-04
IPC分类号： G06F13/00
CPC分类号： G06F12/0831 , G06F2212/1016
摘要： Computer implemented method, system and computer usable program code for processing a data request in a data processing system. A read command requesting data is received from a requesting master device. It is determined whether a cache of a processor can provide the requested data. Responsive to a determination that a cache of a processor can provide the requested data, the requested data is routed to the requesting master device on an intervention data bus of the processor separate from a read data bus and a write data bus of the processor.
摘要翻译： 用于在数据处理系统中处理数据请求的计算机实现的方法，系统和计算机可用程序代码。 从请求主设备接收请求数据的读命令。 确定处理器的高速缓存是否能够提供所请求的数据。 响应于确定处理器的高速缓存可以提供所请求的数据，所请求的数据在与处理器的读取数据总线和写入数据总线分离的处理器的干预数据总线上路由到请求主机设备。
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5.发明授权System on a chip bus with automatic pipeline stage insertion for timing closure 有权系统具有自动流水线插入的片上总线，用于定时关闭公开(公告)号：US06834378B2
公开(公告)日：2004-12-21
申请号：US10264162
申请日：2002-10-03
申请人： Victor Roberts Augsburg , James Norris Dieffenderfer , Bernard Charles Drerup , Richard Gerard Hofmann , Thomas Andrew Sartorius , Barry Joe Wolford
发明人： Victor Roberts Augsburg , James Norris Dieffenderfer , Bernard Charles Drerup , Richard Gerard Hofmann , Thomas Andrew Sartorius , Barry Joe Wolford
IPC分类号： G06F945
CPC分类号： G06F17/5045
摘要： A method of designing a system on a chip (SoC) to operate with varying latencies and frequencies. A layout of the chip is designed with specific placement of devices, including a bus controller, initiator, and target devices. The time for a signal to propagate from a source device to a destination device is determined relative to a default propagation time. A pipeline stage is then inserted into a bus path between said source device and destination device for each additional time the signal takes to propagate. Each device (i.e., initiators, targets, and bus controller) is designed with logic to control a protocol that functions with a variety of response latencies. With the additional logic, the devices do not need to be changed when pipeline stages are inserted in the various paths. Registers are utilized as the pipeline stages that are inserted within the paths.
摘要翻译： 一种设计芯片上的系统（SoC）以在不同的延迟和频率下工作的方法。 芯片的布局设计具有特定的器件布局，包括总线控制器，启动器和目标器件。 相对于默认传播时间确定信号从源设备传播到目的地设备的时间。 然后，在信号需要传播的每个附加时间，将流水线级插入到所述源设备和目的设备之间的总线路径中。 每个设备（即，启动器，目标和总线控制器）被设计为具有控制以各种响应延迟起作用的协议的逻辑。 使用附加逻辑，当管道级插入各种路径时，不需要更改设备。 寄存器被用作插入到路径内的流水线级。
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6.发明授权公开(公告)号：US06826656B2
公开(公告)日：2004-11-30
申请号：US10059537
申请日：2002-01-28
申请人： Victor Roberts Augsburg , James Norris Dieffenderfer , Bernard Charles Drerup , Richard Gerard Hofmann , Thomas Andrew Sartorius , Barry Joe Wolford
发明人： Victor Roberts Augsburg , James Norris Dieffenderfer , Bernard Charles Drerup , Richard Gerard Hofmann , Thomas Andrew Sartorius , Barry Joe Wolford
IPC分类号： G06F1208
CPC分类号： G06F1/3203 , G06F1/3275 , G06F12/0831 , Y02D10/14
摘要： A method and system for reducing power in a snooping cache based environment. A memory may be coupled to a plurality of processing units via a bus. Each processing unit may comprise a cache controller coupled to a cache associated with the processing unit. The cache controller may comprise a segment register comprising N bits where each bit in the segment register may be associated with a segment of memory divided into N segments. The cache controller may be configured to snoop a requested address on the bus. Upon determining which bit in the segment register is associated with the snooped requested address, the segment register may determine if the bit associated with the snooped requested address is set. If the bit is not set, then a cache search may not be performed thereby mitigating the power consumption associated with a snooped request cache search.
摘要翻译： 一种用于在基于窥探缓存的环境中降低功耗的方法和系统。 存储器可以经由总线耦合到多个处理单元。 每个处理单元可以包括耦合到与处理单元相关联的高速缓存器的高速缓存控制器。 高速缓存控制器可以包括包括N个比特的分段寄存器，其中分段寄存器中的每个比特可以与划分成N个分段的一段存储器相关联。 高速缓存控制器可以被配置为窥探总线上的所请求的地址。 一旦确定段寄存器中的哪个位与被窥探的请求地址相关联，则段寄存器可以确定是否设置与被窥探的请求地址相关联的位。 如果该位未设置，则可能不执行高速缓存搜索，从而减轻与窥探请求高速缓存搜索相关联的功耗。
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7.发明授权Method and system for translating a non-native bytecode to a set of codes native to a processor within a computer system 失效用于将非本地字节码转换为计算机系统内的处理器本机的一组代码的方法和系统
公开(公告)号：US5875336A
公开(公告)日：1999-02-23
申请号：US829022
申请日：1997-03-31
IPC分类号： G06F9/455
CPC分类号： G06F9/45504
摘要： A method and system for translating a non-native bytecode to a set of codes native to a processor within a computer system is disclosed. In accordance with the method and system of the present invention, a computer system capable of translating non-native instructions to a set of native instructions is provided that comprises a system memory, a processor, and an instruction set convertor. The system memory is utilized to store non-native instructions and groups of unrelated native instructions. The processor is only capable of processing native instructions. The instruction set convertor, coupled between the system memory and the processor, includes a semantics table and an information table. In response to an instruction fetch from the processor for a non-native instruction in the system memory, the instruction set convertor translates the non-native instruction to a set of native instructions for the processor by accessing both the semantics table and the information table.
摘要翻译： 公开了一种用于将非本地字节码转换为计算机系统内的处理器本机的一组代码的方法和系统。 根据本发明的方法和系统，提供一种能够将非本机指令转换成一组本地指令的计算机系统，其包括系统存储器，处理器和指令集转换器。 系统存储器用于存储非本机指令和一组不相关的本机指令。 处理器只能处理本机指令。 耦合在系统存储器和处理器之间的指令集转换器包括语义表和信息表。 响应于来自处理器的用于系统存储器中的非本地指令的指令获取，指令集转换器通过访问语义表和信息表来将非本地指令转换为处理器的一组本机指令。
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8.发明授权Low latency cadence selectable interface for data transfers between busses of differing frequencies 失效低延迟节奏可选接口，用于不同频率的总线之间的数据传输
公开(公告)号：US5652848A
公开(公告)日：1997-07-29
申请号：US653216
申请日：1996-05-24
CPC分类号： G06F13/28 , G06F13/405
摘要： A bus interface with resources to selectively optimize burst mode data transfers from one bus to another through an automated selection and generation of a cadence. In one form, the cadence is selected based upon memory access latency characteristics, the relative widths of the busses, and the relative clock frequencies of the busses. The selected cadence is provided as a pacing ready signal to the bus receiving the transferred data.
摘要翻译： 具有资源的总线接口，用于通过自动选择和产生节奏来选择性地优化从一个总线到另一个总线的突发模式数据传输。 在一种形式中，基于存储器访问延迟特性，总线的相对宽度和总线的相对时钟频率来选择节奏。 所选择的节奏作为起搏就绪信号被提供给接收传送数据的总线。
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9.发明授权Processor system and methods of triggering a block move using a system bus write command initiated by user code 失效使用由用户代码启动的系统总线写入命令来触发块移动的处理器系统和方法公开(公告)号：US08281075B2
公开(公告)日：2012-10-02
申请号：US12423355
申请日：2009-04-14
申请人： Lakshminarayana Baba Arimilli , Brian Mitchell Bass , David Wayne Cummings , Bernard Charles Drerup , Guy Lynn Guthrie , Ronald Nick Kalla , Hugh Shen , Michael Steven Siegel , William John Starke , Derek Edward Williams
发明人： Lakshminarayana Baba Arimilli , Brian Mitchell Bass , David Wayne Cummings , Bernard Charles Drerup , Guy Lynn Guthrie , Ronald Nick Kalla , Hugh Shen , Michael Steven Siegel , William John Starke , Derek Edward Williams
CPC分类号： G06F12/1458 , G06F9/30047 , G06F9/30087 , G06F12/0893
摘要： A technique for triggering a system bus write command with user code includes identifying a specific store-type instruction in a user instruction sequence. The specific store-type instruction is converted into a specific request-type command, which is configured to include core permission controls (that are stored in core configuration registers of a processor core by a trusted kernel) and user created data (stored in a cache memory). Slave devices are configured through register space (that is only accessible by the trusted kernel) with respective slave permission controls. The specific request-type command is then transmitted from the cache memory, via a system bus. In this case, the slave devices that receive the specific request-type command process the specific request-type command when the core permission controls are the same as the respective slave permission controls. The trusted kernel may be included in a hypervisor or an operating system.
摘要翻译： 用户代码触发系统总线写命令的技术包括识别用户指令序列中的特定存储型指令。 特定存储型指令被转换成特定的请求类型命令，其被配置为包括核心权限控制（存储在可信内核中的处理器核心的核心配置寄存器中）和用户创建的数据（存储在高速缓存中） 记忆）。 从设备通过具有相应从属权限控制的寄存器空间（可由可信内核访问）进行配置。 然后，经由系统总线从高速缓冲存储器发送特定的请求类型命令。 在这种情况下，当核心权限控制与相应从属许可控制相同时，接收特定请求类型命令的从设备处理特定请求类型命令。 可信内核可能包含在管理程序或操作系统中。
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公开(公告)号：US20110074386A1
公开(公告)日：2011-03-31
申请号：US12963950
申请日：2010-12-09
IPC分类号： G01R19/00
CPC分类号： G06F13/4027
摘要： The present invention provides for a system comprising a peripheral component interface (PCI) host bridge. The PCI host bridge is configured to be coupled to a PCI bus, and to receive a system reset signal, to generate a PCI bus reset signal based on the received system reset signal, to detect a PCI operational mode of the PCI bus, and to generate a voltage indicator signal based on the detected PCI operational mode. A voltage regulator is coupled to the PCI host bridge and configured to receive the voltage indicator signal and to regulate a signaling voltage for the PCI bus based on the voltage indicator signal.
摘要翻译： 本发明提供一种包括外围组件接口（PCI）主机桥的系统。 PCI主机桥被配置为耦合到PCI总线，并且接收系统复位信号，以基于接收到的系统复位信号产生PCI总线复位信号，以检测PCI总线的PCI操作模式，并且 基于检测到的PCI操作模式生成电压指示器信号。 电压调节器耦合到PCI主机桥，并被配置为接收电压指示器信号并且基于电压指示器信号来调节用于PCI总线的信令电压。
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