公开(公告)号：US20130063293A1

公开(公告)日：2013-03-14

申请号：US13483704

申请日：2012-05-30

申请人： Zhongxuan Zhang ,  Bernard Ginetti

发明人： Zhongxuan Zhang ,  Bernard Ginetti

IPC分类号： H03M3/02

CPC分类号： H03M7/3002 ,  H03M7/3004

摘要： Digital input words are received in parallel by a parallel digital-to-digital sigma-delta modulator. Error words corresponding to quantization error are added in parallel to the input words to form encoded data words. The encoded data words are quantized into parallel output words and the error words resulting from such quantization are distributed across parallel modulator stages to effect a predetermined quantization error spectral distribution. The quantized output words are output in parallel.

摘要翻译： 数字输入字由并行数字Σ-Δ调制器并行接收。 对应于量化误差的错误字与输入字并行地添加以形成编码数据字。 编码数据字被量化为并行输出字，并且由这种量化产生的误差字分布在并行调制器级上，以实现预定的量化误差频谱分布。 量化输出字并行输出。

公开(公告)号：US08847803B2

公开(公告)日：2014-09-30

申请号：US13483704

申请日：2012-05-30

申请人： Zhongxuan Zhang ,  Bernard Ginetti

发明人： Zhongxuan Zhang ,  Bernard Ginetti

IPC分类号： H03M3/00 ,  H03M7/30

CPC分类号： H03M7/3002 ,  H03M7/3004

摘要： Digital input words are received in parallel by a parallel digital-to-digital sigma-delta modulator. Error words corresponding to quantization error are added in parallel to the input words to form encoded data words. The encoded data words are quantized into parallel output words and the error words resulting from such quantization are distributed across parallel modulator stages to effect a predetermined quantization error spectral distribution. The quantized output words are output in parallel.

摘要翻译： 数字输入字由并行数字Σ-Δ调制器并行接收。 对应于量化误差的错误字与输入字并行地添加以形成编码数据字。 编码数据字被量化为并行输出字，并且由这种量化产生的误差字分布在并行调制器级上，以实现预定的量化误差频谱分布。 量化输出字并行输出。

公开(公告)号：US20130064324A1

公开(公告)日：2013-03-14

申请号：US13484485

申请日：2012-05-31

申请人： Bernard Ginetti ,  Zhongxuan Zhang

发明人： Bernard Ginetti ,  Zhongxuan Zhang

IPC分类号： H04B15/00 ,  H04L27/12

CPC分类号： H03M3/41 ,  H03C3/00 ,  H03M7/3017 ,  H03M7/3026 ,  H03M7/304 ,  H04L27/04

摘要： An arbitrary modulation frequency of a modulating signal is selected. The modulating signal is applied to an information-bearing signal, where such modulation is carried out through digital signal processing operations. The digitally modulated signal is resolution-reduced and the quantization noise introduced by such is shaped to locate a spectral null in the noise transfer function of the resolution reducing modulator at the modulation frequency. Thus, the modulation frequency can be selected independently of the clock frequency at which the resolution-reduced samples are converted to an analog signal.

摘要翻译： 选择调制信号的任意调制频率。 调制信号被应用于信息承载信号，其中通过数字信号处理操作进行这种调制。 数字调制信号是分辨率降低的，并且由此引入的量化噪声被形成为在调制频率下在分辨率降低调制器的噪声传递函数中定位频谱零点。 因此，可以独立于将分辨率降低的采样转换为模拟信号的时钟频率来选择调制频率。

公开(公告)号：US08750413B2

公开(公告)日：2014-06-10

申请号：US13484485

申请日：2012-05-31

申请人： Bernard Ginetti ,  Zhongxuan Zhang

发明人： Bernard Ginetti ,  Zhongxuan Zhang

IPC分类号： H04K1/02 ,  H04L25/03 ,  H04L25/49

CPC分类号： H03M3/41 ,  H03C3/00 ,  H03M7/3017 ,  H03M7/3026 ,  H03M7/304 ,  H04L27/04

摘要： An arbitrary modulation frequency of a modulating signal is selected. The modulating signal is applied to an information-bearing signal, where such modulation is carried out through digital signal processing operations. The digitally modulated signal is resolution-reduced and the quantization noise introduced by such is shaped to locate a spectral null in the noise transfer function of the resolution reducing modulator at the modulation frequency. Thus, the modulation frequency can be selected independently of the clock frequency at which the resolution-reduced samples are converted to an analog signal.

摘要翻译： 选择调制信号的任意调制频率。 调制信号被应用于信息承载信号，其中通过数字信号处理操作进行这种调制。 数字调制信号是分辨率降低的，并且由此引入的量化噪声被形成为在调制频率下在分辨率降低调制器的噪声传递函数中定位频谱零点。 因此，可以独立于将分辨率降低的采样转换为模拟信号的时钟频率来选择调制频率。

公开(公告)号：US06311318B1

公开(公告)日：2001-10-30

申请号：US09353306

申请日：1999-07-13

申请人： Laurent Souef ,  Jerome Bombal ,  Bernard Ginetti

发明人： Laurent Souef ,  Jerome Bombal ,  Bernard Ginetti

IPC分类号： G06F1750

CPC分类号： G01R31/318342

摘要： A computer implemented circuit synthesis system includes a memory, an automatic test pattern generation (ATPG) algorithm, and processing circuitry. The memory is configured to provide a database, and is operative to store a netlist including nets of an integrated circuit under design. The automatic test pattern generation (ATPG) algorithm is operative to design and test an integrated circuit design. The processing circuitry is configured to reduce layout area used during scan insertion, and is operative to: a) identify logic registers of a proposed integrated circuit design that are stitched as a shift register; b) use the ATPG algorithm to transform identified logical registers into scan equivalent logical registers; c) stitch scan equivalent logical registers in an order in which the scan equivalent logical registers were stitched; d) identify stitched scan equivalent logical registers having a same net on both an SI port and a D port; and e) replace the stitched scan equivalent logical registers having the same net on both the SI port and D port. A method is also provided for reducing layout area during test insertion when using an ATPG program to design an integrated circuit having design-for-testability features.

摘要翻译： 计算机实现的电路合成系统包括存储器，自动测试模式生成（ATPG）算法和处理电路。 存储器被配置为提供数据库，并且可操作地存储包括设计中的集成电路的网络的网表。 自动测试模式生成（ATPG）算法可用于设计和测试集成电路设计。 处理电路被配置为减少在扫描插入期间使用的布局区域，并且可操作以：a）识别作为移位寄存器缝合的所提出的集成电路设计的逻辑寄存器; b）使用ATPG算法将识别的逻辑寄存器转换为扫描等效逻辑寄存器; c）以扫描等效逻辑寄存器被缝合的顺序针对等效的逻辑寄存器进行扫描; d）在SI端口和D端口上识别具有相同网络的缝合扫描等效逻辑寄存器; 和e）在SI端口和D端口上替换具有相同网络的缝合扫描等效逻辑寄存器。 还提供了一种方法，用于在使用ATPG程序设计具有设计可测试性特征的集成电路时减少测试插入期间的布局面积。

公开(公告)号：US06202183B1

公开(公告)日：2001-03-13

申请号：US09109848

申请日：1998-07-02

申请人： Bernard Ginetti ,  Christian Zotier ,  Olaf Granzow

发明人： Bernard Ginetti ,  Christian Zotier ,  Olaf Granzow

IPC分类号： G01R3128

CPC分类号： G01R31/318536 ,  G01R31/3167

摘要： An improved system and method to ensure the testability of any analog cell embedded in a mixed signal IC is described wherein the testability is independent of the core logic of that IC, which does not require the dedication of any pin solely to the testing of that IC. A uniform analog test access port design simplifies chip layout, greatly reduces the nunber of MUXed pins required, and allows generation of an analog test program for the total chip which is a simple concatenation and re-use of the individual analog cell test programs.

摘要翻译： 描述了一种改进的系统和方法，以确保嵌入在混合信号IC中的任何模拟单元的可测试性，其中可测试性独立于该IC的核心逻辑，其不需要专门针对该IC的测试 。 统一的模拟测试访问端口设计简化了芯片布局，大大降低了所需的多路复用引脚的Nubber，并允许为总芯片生成模拟测试程序，这是单个模拟单元测试程序的简单连接和重新使用。

公开(公告)号：US5831566A

公开(公告)日：1998-11-03

申请号：US643894

申请日：1996-05-07

申请人： Bernard Ginetti

发明人： Bernard Ginetti

IPC分类号： H03M1/68 ,  H03M1/76 ,  H03M1/66

CPC分类号： H03M1/682 ,  H03M1/765

摘要： A low voltage digital-to-analog converter (DAC) uses a resistor string to divide a supply voltage. The voltage output for the DAC is fixed at an intermediary node in the resistor string, and NMOS and PMOS transistors are used to switch in V.sub.SS and V.sub.DD respectively to nodes in the resistor string such that the NMOS and PMOS transistors are operated where they are most conductive. A decoder is used to decode the digital input to control the switches. One switch from each set of NMOS and PMOS transistors is activated for a given input, or thermometric decoding of the input is used to activate more than one switch from each set to preserve monotonicity. In an alternative embodiment, when matching of the resistors can be assumed, a two-step decoding process is used. An LSB decoder decodes the least significant bits of the digital input and controls how V.sub.DD is applied to a bank of LSB resistors through PMOS transistors, and how V.sub.SS is applied to a second bank of LSB resistors through NMOS transistors. The output from each of these LSB banks lead into to a first MSB bank of resistors and a second bank of MSB resistors, respectively. An MSB decoder decodes the most significant bits of the digital input and controls how the output from the first LSB bank is applied to the first bank of MSB resistors through PMOS transistors, and how the output from the second LSB bank is applied to the second bank of MSB resistors through NMOS transistors. Each MSB resistor is greater than seven LSB resistors in series, and the maximum impedance difference between switches is smaller than an LSB resistor in order to preserve monotonicity of the DAC.

摘要翻译： 低压数模转换器（DAC）使用电阻串来分压电源电压。 DAC的电压输出固定在电阻串中的中间节点，而NMOS和PMOS晶体管分别用于将VSS和VDD分别切换到电阻串中的节点，以使NMOS和PMOS晶体管工作在最大的位置 导电。 解码器用于解码数字输入以控制开关。 对于给定的输入，每一组NMOS和PMOS晶体管的一个开关被激活，或者输入的温度解码用于激活来自每一组的多于一个的开关以保持单调性。 在替代实施例中，当可以假定电阻器的匹配时，使用两步解码处理。 LSB解码器解码数字输入的最低有效位，并控制如何通过PMOS晶体管将VDD施加到一组LSB电阻，以及如何通过NMOS晶体管将VSS应用于第二组LSB电阻。 这些LSB组中的每一个的输出分别导入第一MSB电阻组和第二组MSB电阻。 MSB解码器解码数字输入的最高有效位，并且控制来自第一LSB组的输出如何通过PMOS晶体管施加到第一组MSB电阻器，以及如何将来自第二LSB组的输出施加到第二组 的MSB电阻通过NMOS晶体管。 每个MSB电阻大于串联的7 LSB电阻，开关之间的最大阻抗差小于LSB电阻，以保持DAC的单调性。

公开(公告)号：US20100321220A1

公开(公告)日：2010-12-23

申请号：US12489778

申请日：2009-06-23

申请人： Bernard Ginetti

发明人： Bernard Ginetti

IPC分类号： H03M1/12

CPC分类号： H03M1/442

摘要： The present invention discloses a 1-bit cell circuit used in a pipelined analog to digital converter. The 1-bit cell circuit comprises a reference buffer for providing a reference voltage; a sample and charge transfer circuit for receiving an input signal to generate an output signal; and a dump circuit for dumping said reference voltage; wherein said reference buffer selectively connects to one of said sample and charge transfer circuit and said dump circuit according to said input signal.

摘要翻译： 本发明公开了一种用于流水线模数转换器的1位单元电路。 1位单元电路包括用于提供参考电压的参考缓冲器; 用于接收输入信号以产生输出信号的采样和电荷转移电路; 以及用于倾倒所述参考电压的倾倒电路; 其中所述参考缓冲器根据所述输入信号选择性地连接到所述采样和电荷转移电路中的一个以及所述转储电路。

公开(公告)号：US07852254B1

公开(公告)日：2010-12-14

申请号：US12489778

申请日：2009-06-23

申请人： Bernard Ginetti

发明人： Bernard Ginetti

IPC分类号： H03M1/12

CPC分类号： H03M1/442

摘要： The present invention discloses a 1-bit cell circuit used in a pipelined analog to digital converter. The 1-bit cell circuit comprises a reference buffer for providing a reference voltage; a sample and charge transfer circuit for receiving an input signal to generate an output signal; and a dump circuit for dumping said reference voltage; wherein said reference buffer selectively connects to one of said sample and charge transfer circuit and said dump circuit according to said input signal.

摘要翻译： 本发明公开了一种用于流水线模数转换器的1位单元电路。 1位单元电路包括用于提供参考电压的参考缓冲器; 用于接收输入信号以产生输出信号的采样和电荷转移电路; 以及用于倾倒所述参考电压的倾倒电路; 其中所述参考缓冲器根据所述输入信号选择性地连接到所述采样和电荷转移电路中的一个以及所述转储电路。

公开(公告)号：US06737904B1

公开(公告)日：2004-05-18

申请号：US09439970

申请日：1999-11-12

申请人： Remi Butaud ,  Bernard Ginetti

发明人： Remi Butaud ,  Bernard Ginetti

IPC分类号： H03K300

CPC分类号： G06F1/04 ,  H04B15/06 ,  H04B2215/067

摘要： A method of producing a clock signal with reduced electromagnetic interference spectral components includes providing a first clock signal; producing a second clock signal by delaying the first clock signal; and generating a jittered clock signal by switching between the first clock signal and the second clock signal at times selected responsive to a random number generator. A GSM phone comprises a clock configured to produce a first clock signal; a delay element coupled to the clock to produce a second clock signal by delaying the first clock signal; a multiplexer coupled to the clock and to the delay element to select between the clock and the delay element; a random number generator coupled to the multiplexer wherein the multiplexer generates a jittered clock signal by switching between the first clock signal and the second clock signal responsive to the random number generator; and a plurality of GSM phone components respectively coupled to the multiplexer to use the jittered clock signal as an input clock for the component.

摘要翻译： 一种产生具有降低的电磁干扰频谱分量的时钟信号的方法包括：提供第一时钟信号; 通过延迟第一时钟信号产生第二时钟信号; 以及通过在响应于随机数发生器选择的时间在第一时钟信号和第二时钟信号之间切换来产生抖动的时钟信号。 GSM电话包括被配置为产生第一时钟信号的时钟; 延迟元件，其耦合到所述时钟，以通过延迟所述第一时钟信号产生第二时钟信号; 耦合到时钟和延迟元件的多路复用器，用于在时钟和延迟元件之间进行选择; 耦合到所述多路复用器的随机数发生器，其中所述多路复用器通过响应于所述随机数发生器在所述第一时钟信号和所述第二时钟信号之间切换来产生抖动时钟信号; 以及分别耦合到多路复用器的多个GSM电话组件，以将抖动的时钟信号用作该组件的输入时钟。