公开(公告)号：US06307792B1

公开(公告)日：2001-10-23

申请号：US09675366

申请日：2000-09-29

申请人： Bertrand Bertrand ,  David Naura ,  Sébastien Zink

发明人： Bertrand Bertrand ,  David Naura ,  Sébastien Zink

IPC分类号： G11C700

CPC分类号： G11C7/12 ,  G11C16/24

摘要： A column register of an integrated circuit memory, notably in EEPROM technology, is utilized in a method of writing a data word of 2p bits in the memory, where p is a non-zero whole number. The method includes the following steps: 1) erasing all the cells of the word; 2) loading 2q data in 2q high-voltage latches (HV1, HV3, HV5, HV7), and loading 2p−2q other data in the 2p−2q low-voltage latches (LV0, LV2, LV4, LV6); and 3) programming 2q cells of the memory (M0, M2, M4, M6) as a function of the data memorized in the 2q high-voltage latches; as well as repeating 2p−q−1 times the following steps: 4) loading, in the 2q high-voltage latches, of 2q other data that were loaded in the 2q low-voltage latches at step 2); and 5) programming 2q other cells of the memory (M1, M3, M5, M7) as a function of the data memorized in the 2q high-voltage latches.

摘要翻译： 集成电路存储器的列寄存器，特别是在EEPROM技术中，用于将2p位的数据字写入存储器的方法，其中p是非零整数。 该方法包括以下步骤：1）擦除单词的所有单元; 2）在2q高压锁存器（HV1，HV3，HV5，HV7）中加载2q数据，并在2p-2q中加载2p-2q其他数据 低压锁存器（LV0，LV2，LV4，LV6）; 和3）根据存储在2q高电压锁存器中的数据来编程存储器（M0，M2，M4，M6）的2q个单元;以及重复2p-q-1次以下步骤：4）加载， 在2q高电压锁存器中，在步骤2）装入2q低压锁存器的2q其他数据; 和5）根据存储在2q高电压锁存器中的数据来编程存储器（M1，M3，M5，M7）的2q个其他单元。

公开(公告)号：US06359822B1

公开(公告)日：2002-03-19

申请号：US09676744

申请日：2000-09-29

申请人： Sébastien Zink ,  Bertrand Bertrand ,  David Naura

发明人： Sébastien Zink ,  Bertrand Bertrand ,  David Naura

IPC分类号： G11C700

CPC分类号： G11C16/10 ,  G11C7/103 ,  G11C16/08 ,  G11C2216/30

摘要： An integrated circuit serial access type memory, notably in EEPROM technology, includes a data input (DI) and a data output (DO), a defined memory plane (MM) organized in memory words, as well as a set (LAT) of column registers, one such register being associated with at least one memory word of the memory. The memory includes a writing circuit and/or a reading circuit. The writing circuit operates, during an operation for writing a binary word in a given memory word (M0-M7), for loading the binary data of the binary word received in series at the data input (DI) directly into respective storage and switching latches (HV0-HV7) of the column register (R1) associated with the memory word (M0-M7). The reading circuit operates, during an operation for reading a binary word in a memory word, for reading successively the binary data stored in the memory cells of the memory word and for delivering directly, in serial form, each binary data read to the data output (DO) of the memory.

摘要翻译： 集成电路串行访问型存储器，特别是在EEPROM技术中，包括数据输入（DI）和数据输出（DO），以存储器字组织的定义的存储器平面（MM）以及列（LAT）的列 寄存器，一个这样的寄存器与存储器的至少一个存储器字相关联。 存储器包括写入电路和/或读取电路。 在用于将给定存储字（M0-M7）中的二进制字写入的操作期间，写电路用于将数据输入（DI）上串联接收的二进制字的二进制数据直接加载到相应的存储和切换锁存器 （M0-M7）相关联的列寄存器（R1）的（HV0-HV7）。 读取电路在用于读取存储器字中的二进制字的操作期间连续读取存储在存储器字的存储器单元中的二进制数据，并且以串行形式直接传送读取到数据输出的每个二进制数据 （DO）的记忆。

公开(公告)号：US06324117B1

公开(公告)日：2001-11-27

申请号：US09676434

申请日：2000-09-29

申请人： Sébastien Zink ,  Bertrand Bertrand ,  David Naura

发明人： Sébastien Zink ,  Bertrand Bertrand ,  David Naura

IPC分类号： G11C800

CPC分类号： G11C5/066 ,  G11C8/10 ,  G11C2216/30

摘要： The invention proposes a method of selecting a determined access line of a serial access type integrated circuit memory, a determined access line being selectable among a determined group of access lines (AL0-AL7) of the same nature, for example a group of bit lines or a group of word lines, a line code on p bits being respectively associated to each access line of the group, which consists in pre-activating all the access lines of the group, then ofdeactivating progressively the other access lines as a function of the bits (Ai) of the line code of the access line to select received in series via the serial data input of the memory such that, in the end, only the access line to be selected remains activated.

摘要翻译： 本发明提出了一种选择串行接入型集成电路存储器的确定的接入线路的方法，所确定的接入线路可在相同性质的确定的接入线路组（AL0-AL7）之间选择，例如一组位线 或一组字线，p位上的行代码分别与组的每个访问行相关联，其中包括预先激活该组的所有访问行，然后逐渐地将其他访问行的活动作为 通过存储器的串行数据输入串行接收的接入线的线路码的位（Ai），使得最终只有要被选择的接入线保持激活。

公开(公告)号：US06385096B1

公开(公告)日：2002-05-07

申请号：US09952904

申请日：2001-09-13

申请人： Bertrand Bertrand ,  David Naura ,  Sébastien Zink

发明人： Bertrand Bertrand ,  David Naura ,  Sébastien Zink

IPC分类号： G11C700

CPC分类号： G11C7/12 ,  G11C16/24

摘要： A column register of an integrated circuit memory, notably in EEPROM technology, is utilized in a method of writing a data word of 2p bits in the memory, where p is a non-zero whole number. The method includes the following steps: 1) erasing all the cells of the word; 2) loading 2q data in 2q high-voltage latches (HV1, HV3, HV5, HV7), and loading 2p-2q other data in the 2p-2q low-voltage latches (LV0, LV2, LV4, LV6); and 3) programming 2q cells of the memory (M0, M2, M4, M6) as a function of the data memorized in the 2q high-voltage latches; as well as repeating 2p-q−1 times the following steps: 4) loading, in the 2q high-voltage latches, of 2q other data that were loaded in the 2q low-voltage latches at step 2); and 5) programming 2q other cells of the memory (M1, M3, M5, M7) as a function of the data memorized in the 2q high-voltage latches.

摘要翻译： 集成电路存储器的列寄存器，特别是在EEPROM技术中，用于将2p位的数据字写入存储器的方法，其中p是非零整数。 该方法包括以下步骤：1）擦除单词的所有单元; 2）在2q高压锁存器（HV1，HV3，HV5，HV7）中加载2q数据，并在2p-2q中加载2p-2q其他数据 低压锁存器（LV0，LV2，LV4，LV6）; 和3）根据存储在2q高电压锁存器中的数据来编程存储器（M0，M2，M4，M6）的2q个单元;以及重复2p-q-1次以下步骤：4）加载， 在2q高电压锁存器中，在步骤2）装入2q低压锁存器的2q其他数据; 和5）根据存储在2q高电压锁存器中的数据来编程存储器（M1，M3，M5，M7）的2q个其他单元。

公开(公告)号：US07012837B2

公开(公告)日：2006-03-14

申请号：US10903927

申请日：2004-07-31

申请人： David Naura ,  Bertrand Bertrand ,  Mohamad Chehadi

发明人： David Naura ,  Bertrand Bertrand ,  Mohamad Chehadi

IPC分类号： G11C16/04

CPC分类号： G11C16/12 ,  G11C8/08 ,  G11C16/14

摘要： A method is provided for erasing or programming at least one memory cell of a non-volatile memory. According to the method, a state fixation pulse is applied to a floating gate transistor of the memory cell. The state fixation pulse also includes, successively, a portion at a reference voltage, and a state fixation portion at a voltage with sufficient amplitude for the transfer of electrons between the drain and the gate of the floating gate transistor. Additionally, an external adjustment signal is applied to the memory to adjust the state fixation portion to a predetermined duration, and the state fixation portion is adjusted to the predetermined duration in real time as a function of the state of the adjustment signal. Also provided is a non-volatile memory.

摘要翻译： 提供一种用于擦除或编程非易失性存储器的至少一个存储单元的方法。 根据该方法，将状态固定脉冲施加到存储单元的浮栅晶体管。 状态固定脉冲还连续地包括参考电压的一部分，以及具有足够幅度的电压的状态固定部分，用于在浮置栅晶体管的漏极和栅极之间传输电子。 此外，外部调整信号被施加到存储器以将状态固定部分调整到预定的持续时间，并且根据调整信号的状态将状态固定部分实时地调整到预定的持续时间。 还提供了非易失性存储器。

公开(公告)号：US06621737B2

公开(公告)日：2003-09-16

申请号：US10096531

申请日：2002-03-11

申请人： David Naura ,  Bertrand Bertrand ,  Mohamad Chehadi

发明人： David Naura ,  Bertrand Bertrand ,  Mohamad Chehadi

IPC分类号： G11C1606

CPC分类号： G11C16/12

摘要： A circuit produces a voltage for the erasure or programming of a memory cell. The circuit includes a capacitor, and a discharge circuit connected to a first terminal of the capacitor. The discharge circuit includes a first transistor, a drain of which is connected to the first terminal of the capacitor. The first transistor activates the discharge circuit when a discharge signal is received by a gate of the first transistor. The discharge circuit includes a slow discharge arm and a fast discharge arm parallel-connected to the source of the first transistor. The discharge circuit produces a low discharge current or a high discharge current for discharging the capacitor as a function of an operating mode selection signal.

公开(公告)号：US07237157B2

公开(公告)日：2007-06-26

申请号：US10844978

申请日：2004-05-13

申请人： David Naura ,  Bertrand Bertrand ,  Mohamad Chehadi

发明人： David Naura ,  Bertrand Bertrand ,  Mohamad Chehadi

IPC分类号： G11C29/08 ,  G11C29/06

CPC分类号： G11C29/46

摘要： A procedure is provided for identifying an operating mode of a device, such as an EEPROM memory that communicates according to a communication protocol, such as “I2C” (Inter Integrated Circuit). The signal is an “ACK” or “ACKNOWLEDGE” signal. At least one operating mode of a device is identified by a time lag from the time the signal (ACK) is transmitted relative to the time foreseen by the protocol for the signal. This approach can be used to verify that the test mode commands (read or write) have been taken into account correctly.

摘要翻译： 提供了用于识别诸如“I 2 C”（集成内部电路）等通信协议进行通信的EEPROM存储器的装置的操作模式的过程。 信号是“ACK”或“ACKNOWLEDGE”信号。 从信号（ACK）相对于信号协议所预见的时间发送的时间，通过时间滞后来识别设备的至少一个操作模式。 该方法可用于验证测试模式命令（读取或写入）是否被正确地考虑在内。

公开(公告)号：US06714450B2

公开(公告)日：2004-03-30

申请号：US10100511

申请日：2002-03-18

申请人： Bertrand Bertrand ,  Mohamad Chehadi ,  David Naura

发明人： Bertrand Bertrand ,  Mohamad Chehadi ,  David Naura

IPC分类号： G11C1608

CPC分类号： G11C16/12 ,  G11C16/0433

摘要： An electrically programmable and erasable memory includes memory cells connected to word lines and to bit lines arranged in columns. Bit lines selection transistors are driven by bit lines selection signals. Column selection latches each includes a locking element for a column selection signal and a circuit for delivering a gate control signal which depends on the output of the locking element. Each column selection latch delivers, in addition to a gate control signal, a bit lines selection signal. This signal depends on the output of the locking element at least during programming and reading phases of the memory cells.

摘要翻译： 电可编程和可擦除存储器包括连接到字线和排列成列的位线的存储器单元。 位线选择晶体管由位线选择信号驱动。 列选择锁存器各自包括用于列选择信号的锁定元件和用于传送取决于锁定元件的输出的门控制信号的电路。 每个列选择锁存器除了门控制信号之外还提供位线选择信号。 该信号至少在存储器单元的编程和读取阶段期间取决于锁定元件的输出。

公开(公告)号：US06504791B1

公开(公告)日：2003-01-07

申请号：US09660303

申请日：2000-09-12

申请人： David Naura ,  Sebastien Zink ,  Bertrand Bertrand

发明人： David Naura ,  Sebastien Zink ,  Bertrand Bertrand

IPC分类号： G11C800

CPC分类号： G11C16/10

摘要： A method of writing in page mode in an electrically erasable and programmable non-volatile memory includes an initialization phase of writing an information element for the selection of the page in a storage latch associated with a column of the non-volatile memory array, and the writing in a temporary memory of each of the data bits to be written in the page. A write phase includes the selection of rows of the non-volatile memory array according to the contents of the temporary memory. A page mode write circuit includes one latch per column of the non-volatile memory array to contain a page selection information element, and a control logic circuit to give the row selection signals as a function of the contents of the temporary memory in a phase for writing the column of the non-volatile memory array.

摘要翻译： 在电可擦除可编程非易失性存储器中以页模式写入的方法包括：在与非易失性存储器阵列的列相关联的存储锁存器中写入用于页的选择的信息元素的初始化阶段，以及 在临时存储器中写入要写入页面的每个数据位。 写入阶段包括根据临时存储器的内容来选择非易失性存储器阵列的行。 页面模式写入电路包括每列非易失性存储器阵列中的一个锁存器以包含页面选择信息元素，以及控制逻辑电路，用于以相位为单位给出作为临时存储器的内容的函数的行选择信号 写入非易失性存储器阵列的列。

公开(公告)号：US20050207230A1

公开(公告)日：2005-09-22

申请号：US10903927

申请日：2004-07-31

申请人： David Naura ,  Bertrand Bertrand ,  Mohamad Chehadi

发明人： David Naura ,  Bertrand Bertrand ,  Mohamad Chehadi

IPC分类号： G11C8/08 ,  G11C16/12 ,  G11C16/14 ,  G11C16/04 ,  G11C7/00

CPC分类号： G11C16/12 ,  G11C8/08 ,  G11C16/14

摘要： A method is provided for erasing or programming at least one memory cell of a non-volatile memory. According to the method, a state fixation pulse is applied to a floating gate transistor of the memory cell. The state fixation pulse also includes, successively, a portion at a reference voltage, and a state fixation portion at a voltage with sufficient amplitude for the transfer of electrons between the drain and the gate of the floating gate transistor. Additionally, an external adjustment signal is applied to the memory to adjust the state fixation portion to a predetermined duration, and the state fixation portion is adjusted to the predetermined duration in real time as a function of the state of the adjustment signal. Also provided is a non-volatile memory.

摘要翻译： 提供一种用于擦除或编程非易失性存储器的至少一个存储单元的方法。 根据该方法，将状态固定脉冲施加到存储单元的浮栅晶体管。 状态固定脉冲还连续地包括参考电压的一部分，以及具有足够幅度的电压的状态固定部分，用于在浮置栅晶体管的漏极和栅极之间传输电子。 此外，外部调整信号被施加到存储器以将状态固定部分调整到预定的持续时间，并且根据调整信号的状态将状态固定部分实时地调整到预定的持续时间。 还提供了非易失性存储器。