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    Minimizing plating stub reflections in a chip package using capacitance
    5.
    发明授权
    Minimizing plating stub reflections in a chip package using capacitance 有权
    使用电容最小化芯片封装中的电镀短截线反射

    公开(公告)号：US08830690B2

    公开(公告)日：2014-09-09

    申请号：US12237444

    申请日：2008-09-25

    Applicant: Bhyrav M Mutnury ,  Moises Cases ,  Nanju Na ,  Tae Hong Kim

    Inventor： Bhyrav M Mutnury ,  Moises Cases ,  Nanju Na ,  Tae Hong Kim

    IPC: H05K1/18 ,  H05K1/02 ,  H05K1/16 ,  H05K3/24

    CPC classification number: H01L21/4853 ,  C25D5/02 ,  H01L24/73 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2924/14 ,  H01L2924/15311 ,  H05K1/0231 ,  H05K1/162 ,  H05K3/242 ,  H05K2203/049 ,  H01L2924/00012 ,  H01L2924/00

    Abstract: Embodiments of the present invention are directed to shifting the resonant frequency in a high-frequency chip package away from an operational frequency by connecting a capacitance between an open-ended plating stub and ground. One embodiment provides a multi-layer substrate for interfacing a chip with a printed circuit board. A first outer layer provides a chip mounting location. A signal interconnect is spaced from the chip mounting location, and a signal trace extends from near the chip mounting location to the signal interconnect. A chip mounted at the chip mounting location may be connected to the signal trace by wirebonding. A plating stub extends from the signal interconnect, such as to a periphery of the substrate. A capacitor is used to capacitively couple the plating stub to a ground layer.

    Abstract translation: 本发明的实施例涉及通过连接开放式电镀短截线和接地之间的电容来将高频芯片封装中的谐振频率从工作频率移开。 一个实施例提供了用于将芯片与印刷电路板接口的多层基板。 第一外层提供了芯片安装位置。 信号互连与芯片安装位置间隔开，并且信号迹线从芯片安装位置附近延伸到信号互连。 安装在芯片安装位置的芯片可以通过引线键合连接到信号迹线。 电镀短截线从信号互连延伸到衬底的周围。 电容器用于将电镀端子电容耦合到接地层。

    Packages and Methods for Mitigating Plating Stub Effects
    6.
    发明申请
    Packages and Methods for Mitigating Plating Stub Effects 审中-公开
    减轻电镀桩影响的包装和方法

    公开(公告)号：US20110103030A1

    公开(公告)日：2011-05-05

    申请号：US12610413

    申请日：2009-11-02

    Applicant: Moises Cases ,  Tae Hong Kim ,  Bhyrav M. Mutnury ,  Nanju Na

    Inventor： Moises Cases ,  Tae Hong Kim ,  Bhyrav M. Mutnury ,  Nanju Na

    IPC: H01L23/52 ,  H01L21/60 ,  H05K7/00

    CPC classification number: H01L23/647 ,  H01L23/49838 ,  H01L23/66 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/19105 ,  H01L2924/3011 ,  H01L2924/00014

    Abstract: Packages and methods for mitigating plating stub effects. The semiconductor package includes an interposer substrate having a first side, a second side, a peripheral edge connecting the first side with the second side, a signal line on the first side, and an electrode pad on the first side. A semiconductor element is mounted on the first side of the interposer substrate. The semiconductor element is connected with the electrode pad by the signal line. A terminating resistor is mounted on the interposer substrate. A plating stub, which is located on the interposer substrate, has a first end portion that terminates near the peripheral edge of the interposer substrate and a second end portion that is electrically connected to the electrode. The first end portion is electrically connected through the terminating resistor to an electrical ground.

    Abstract translation: 用于减轻电镀桩效应的包装和方法。 半导体封装包括具有第一侧，第二侧，连接第一侧与第二侧的周边边缘，第一侧上的信号线和第一侧上的电极焊盘的插入器基板。 半导体元件安装在插入器基板的第一侧上。 半导体元件通过信号线与电极焊盘连接。 终端电阻器安装在插入器基板上。 位于内插基板上的电镀短截线具有在中介基板的周缘附近终止的第一端部和与该电极电连接的第二端部。 第一端部通过终端电阻器电连接到电接地。

    Controlling plating stub reflections in a chip package
    7.
    发明授权
    Controlling plating stub reflections in a chip package 失效
    控制芯片封装中的电镀短截线反射

    公开(公告)号：US08402406B2

    公开(公告)日：2013-03-19

    申请号：US12979745

    申请日：2010-12-28

    Applicant: Moises Cases ,  Bhyrav M. Mutnury ,  Nanju Na ,  Terence Rodrigues

    Inventor： Moises Cases ,  Bhyrav M. Mutnury ,  Nanju Na ,  Terence Rodrigues

    IPC: G06F17/50 ,  G06F9/455 ,  H01L23/02 ,  H01L21/00 ,  H01R9/00

    CPC classification number: G06F17/5068 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2924/15311 ,  H01L2924/3011 ,  H01L2924/00014 ,  H01L2924/00

    Abstract: Methods, apparatuses, and computer program products are disclosed for controlling plating stub reflections in a chip package. In one embodiment, a resonance optimizer determines performance characteristics of a bond wire that connects a chip to a substrate of a semiconductor chip mount. In this embodiment, the resonance optimizer selects, based on the performance characteristics of the bond wire, a line width for an open-ended plating stub that extends from a signal interconnect of the substrate to a periphery of the substrate, The resonance optimizer also generates a design of signal traces for the substrate, where the signal traces include the open-ended plating stub with the selected line width.

    Abstract translation: 公开了用于控制芯片封装中的电镀短截线反射的方法，装置和计算机程序产品。 在一个实施例中，谐振优化器确定将芯片连接到半导体芯片基座的衬底的接合线的性能特性。 在该实施例中，谐振优化器基于接合线的性能特性，选择从衬底的信号互连延伸到衬底的周边的开放式电镀短截线的线宽度。谐振优化器还产生 用于衬底的信号迹线的设计，其中信号迹线包括具有所选线宽的开口电镀短截线。

    Controlling Plating Stub Reflections In A Chip Package
    8.
    发明申请
    Controlling Plating Stub Reflections In A Chip Package 失效
    控制芯片封装中的电镀短截线反射

    公开(公告)号：US20120167033A1

    公开(公告)日：2012-06-28

    申请号：US12979745

    申请日：2010-12-28

    Applicant: Moises Cases ,  Bhyrav M. Mutnury ,  Nanju Na ,  Terence Rodrigues

    Inventor： Moises Cases ,  Bhyrav M. Mutnury ,  Nanju Na ,  Terence Rodrigues

    IPC: G06F17/50

    CPC classification number: G06F17/5068 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2924/15311 ,  H01L2924/3011 ,  H01L2924/00014 ,  H01L2924/00

    Abstract: Methods, apparatuses, and computer program products are disclosed for controlling plating stub reflections in a chip package. Embodiments include determining, by a resonance optimizer, performance characteristics of a bond wire, the bond wire connecting a chip to a substrate of a semiconductor chip mount; based on the performance characteristics of the bond wire, selecting, by the resonance optimizer, a line width for an open-ended plating stub, the open-ended plating stub extending from a signal interconnect of the substrate to a periphery of the substrate; and generating, by the resonance optimizer, a design of signal traces for the substrate, the signal traces including the open-ended plating stub with the selected line width.

    Abstract translation: 公开了用于控制芯片封装中的电镀短截线反射的方法，装置和计算机程序产品。 实施例包括通过谐振优化器确定接合线的性能特征，将芯片连接到半导体芯片基座的衬底的接合线; 基于所述接合线的性能特性，通过所述共振优化器选择所述开口电镀短截线的线宽，所述开口电镀短截线从所述基板的信号互连延伸到所述基板的周围; 并且通过所述谐振优化器产生用于所述衬底的信号迹线的设计，所述信号迹线包括具有所选线宽度的开放式电镀短截线。

    Reducing plating stub reflections in a chip package using resistive coupling
    9.
    发明授权
    Reducing plating stub reflections in a chip package using resistive coupling 失效
    使用电阻耦合减少芯片封装中的电镀短截线反射

    公开(公告)号：US08102042B2

    公开(公告)日：2012-01-24

    申请号：US12630720

    申请日：2009-12-03

    Applicant: Moises Cases ,  Bhyrav M. Mutnury ,  Nanju Na

    Inventor： Moises Cases ,  Bhyrav M. Mutnury ,  Nanju Na

    IPC: H01L23/498

    CPC classification number: H05K1/0234 ,  H01L24/73 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/73265 ,  H01L2924/14 ,  H01L2924/15311 ,  H05K3/242 ,  H05K2203/049 ,  Y10T29/49128 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/00

    Abstract: Improving signal quality in a high-frequency chip package by resistively connecting an open-ended plating stub to ground. One embodiment provides a multi-layer substrate for interfacing a chip with a printed circuit board. A conductive first layer provides a chip mounting location. A signal interconnect is spaced from the chip mounting location, and a signal trace extends from near the chip mounting location to the signal interconnect. A chip mounted at the chip mounting location may be connected to the signal trace by wirebonding. A plating stub extends from the signal interconnect, such as to a periphery of the substrate. A resistor is used to resistively couple the plating stub to a ground layer.

    Abstract translation: 通过将开口电镀短截线电阻连接到地来提高高频芯片封装中的信号质量。 一个实施例提供了用于将芯片与印刷电路板接口的多层基板。 导电第一层提供芯片安装位置。 信号互连与芯片安装位置间隔开，并且信号迹线从芯片安装位置附近延伸到信号互连。 安装在芯片安装位置的芯片可以通过引线键合连接到信号迹线。 电镀短截线从信号互连延伸到衬底的周围。 电阻器用于将电镀端子电阻耦合到接地层。

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