公开(公告)号：US6080662A

公开(公告)日：2000-06-27

申请号：US186346

申请日：1998-11-04

申请人： Bi-Ling Chen ,  Erik S. Jeng ,  Hao-Chieh Liu

发明人： Bi-Ling Chen ,  Erik S. Jeng ,  Hao-Chieh Liu

IPC分类号： H01L21/311 ,  H01L21/60 ,  H01L21/768 ,  H01L21/4763 ,  H01L21/302 ,  H01L21/461

CPC分类号： H01L21/76816 ,  H01L21/31116

摘要： A method for forming multi-level contact holes in a semiconductor structure is disclosed. The semiconductor structure includes a dielectric layer overlying a silicon substrate, a silicon nitride layer within the dielectric layer, the silicon nitride layer overlying a first conductive layer, a silicon oxynitride layer within the dielectric layer, the silicon oxynitride layer overlying a second conductive layer, and a plate poly layer. The method comprises: using a first etching step to etch through the dielectric layer to reach the silicon nitride layer as well as reach the silicon oxynitride layer, the first etching step using a combination of a first gas mixture and a first gas, the first gas mixture comprising a combination of N.sub.2, CO and Ar. The first gas includes C.sub.4 F.sub.8, CH.sub.3 F and O.sub.2, the flow rate ratio of the first gas C.sub.4 F.sub.8 /CH.sub.3 F/O.sub.2 is about 6:1:3. The flow rate of each component of the first gas mixture is that, the flow rate of N.sub.2 is about 0-20 sccm, the flow rate of CO is about 0-200 sccm, and the flow rate of Ar is about 100-600 sccm. In addition, the flow rate of each component of the first gas is that, the flow rate of C.sub.4 F.sub.8 is about 8-40 sccm, the flow rate of CH.sub.3 F is about 1-7 sccm, and the flow rate of O.sub.2 is about 0-20 sccm. Then using a second etching step to etch through the silicon nitride layer to reach the first conductive layer, the second etching step also etching through the silicon oxynitride layer to reach the second conductive layer. The second etching step uses a combination of the first gas mixture and a second gas, the second gas comprising CH.sub.3 F of the flow rate of about 3-14 sccm.

摘要翻译： 公开了一种在半导体结构中形成多层接触孔的方法。 半导体结构包括覆盖硅衬底的电介质层，电介质层内的氮化硅层，覆盖在第一导电层上的氮化硅层，介电层内的氧氮化硅层，覆盖在第二导电层上的氧氮化硅层， 和板状多层。 该方法包括：使用第一蚀刻步骤来蚀刻穿过介电层以到达氮化硅层以及到达氧氮化硅层，第一蚀刻步骤使用第一气体混合物和第一气体的组合，第一气体 混合物包含N2，CO和Ar的组合。 第一气体包括C4F8，CH3F和O2，第一气体C4F8 / CH3F / O2的流量比约为6：1：3。 第一气体混合物的每个组分的流速是N 2的流量约为0-20sccm，CO的流量约为0-200sccm，Ar的流速约为100-600sccm 。 另外，第一气体的各成分的流量为C4F8的流量为约8〜40sccm，CH 3 F的流量为约1-7sccm，O 2的流量约为0〜 20 sccm。 然后使用第二蚀刻步骤蚀刻穿过氮化硅层以到达第一导电层，第二蚀刻步骤还蚀刻穿过氮氧化硅层以到达第二导电层。 第二蚀刻步骤使用第一气体混合物和第二气体的组合，第二气体包含流速为约3-14sccm的CH 3 F.

公开(公告)号：US06565759B1

公开(公告)日：2003-05-20

申请号：US09375203

申请日：1999-08-16

申请人： Bi-Ling Chen ,  Erik S. Jeng ,  Hao-Chieh Liu

发明人： Bi-Ling Chen ,  Erik S. Jeng ,  Hao-Chieh Liu

IPC分类号： H01G900

CPC分类号： H01L21/02274 ,  H01L21/02129 ,  H01L21/31116 ,  H01L21/31625

摘要： A method for etching a pattern within a silicon containing dielectric layer upon a substrate employed within a microelectronics fabrication, employing a plasma activated reactive gas mixture, with layer material etch rate, etch rate ratio and pattern aspect ratio controlled by controlling the gas composition. There is provided a silicon substrate formed upon it a patterned microelectronics layer over which is formed a silicon containing dielectric layer. There is placed the silicon substrate within a reactor chamber equipped with electrodes which is evacuated. There is then filled the reactor chamber with a reactive gas mixture consisting of an oxidizing gas and two reactive gases. There may be optionally included in the reactive gas mixture nitrogen and inert gases for control purposes, but excluded from the reactive gas mixture are oxidizing gases containing carbon and oxygen. There is then formed a plasma by supplying high frequency electrical energy to the electrodes within the reactor chamber to bring about a plasma activated reactive gas etching environment, where the conditions may be selected to optimize the desired etch rate and etch rate selectivity.

摘要翻译： 在采用等离子体激活的反应气体混合物的基板上蚀刻含硅介质层内的图案的方法，其中层材料蚀刻速率，蚀刻速率比和通过控制气体成分控制的图案纵横比。 提供了在其上形成图案化的微电子层的硅衬底，在其上形成含硅介电层。 将硅衬底放置在配备有被抽真空的电极的反应器室内。 然后用反应气体混合物填充反应器室，该气体混合物由氧化气体和两种反应性气体组成。 为了控制目的，反应气体混合物中可以任选地包含氮气和惰性气体，但是从反应性气体混合物排除的是含有碳和氧的氧化气体。 然后通过向反应器室内的电极提供高频电能来形成等离子体，以产生等离子体激活的反应气体蚀刻环境，其中可以选择条件以优化所需的蚀刻速率和蚀刻速率选择性。

公开(公告)号：US6103588A

公开(公告)日：2000-08-15

申请号：US122307

申请日：1998-07-24

申请人： Erik S. Jeng ,  Bi-Ling Chen ,  Hao-Chieh Liu

发明人： Erik S. Jeng ,  Bi-Ling Chen ,  Hao-Chieh Liu

IPC分类号： H01L21/60 ,  H01L21/20

CPC分类号： H01L21/76897

摘要： The present invention includes forming a first conductive layer on a semiconductor substrate, and forming a first dielectric layer on the first conductive layer. After patterning to etch the first dielectric layer and the first conductive layer, a second dielectric layer is formed on the semiconductor substrate and the first dielectric layer. Next, the second dielectric layer is anisotropically etched back to form a spacer on sidewalls of the first dielectric layer and the first conductive layer. A first silicon oxide layer is then formed over the semiconductor substrate, the first dielectric layer, and the spacer, followed by forming a photoresist layer on the first silicon oxide layer. A predetermined thickness of the first silicon oxide layer is removed by using the photoresist layer as a mask, and a polymer layer is then formed on the photoresist layer and the first silicon oxide layer. The polymer layer is anisotropically etched back to form a polymer spacer on sidewalls of the photoresist layer and the first silicon oxide layer. The first silicon oxide layer is then anisotropically etched back by using the polymer spacer as a mask to expose surface of the semiconductor substrate, wherein the spacer and the first dielectric layer are used for facilitating self-aligned etching. A second conductive layer is formed over the semiconductor substrate, surface of the second silicon oxide layer being exposed, and a second silicon oxide layer is formed over the second conductive layer and the first silicon oxide layer. Finally, a portion of the second silicon oxide layer is patterned to expose a portion of the second conductive layer, thereby forming the contact hole in the second oxide layer.

摘要翻译： 本发明包括在半导体衬底上形成第一导电层，并在第一导电层上形成第一电介质层。 在图案化以蚀刻第一介电层和第一导电层之后，在半导体衬底和第一介电层上形成第二电介质层。 接下来，将第二介电层各向异性地回蚀以在第一介电层和第一导电层的侧壁上形成间隔物。 然后在半导体衬底，第一介电层和间隔物上形成第一氧化硅层，随后在第一氧化硅层上形成光致抗蚀剂层。 通过使用光致抗蚀剂层作为掩模去除第一氧化硅层的预定厚度，然后在光致抗蚀剂层和第一氧化硅层上形成聚合物层。 聚合物层被各向异性地回蚀刻以在光致抗蚀剂层和第一氧化硅层的侧壁上形成聚合物间隔物。 然后通过使用聚合物间隔物作为掩模将第一氧化硅层各向异性地回蚀以暴露半导体衬底的表面，其中间隔物和第一介电层用于促进自对准蚀刻。 在半导体衬底上形成第二导电层，暴露第二氧化硅层的表面，在第二导电层和第一氧化硅层之上形成第二氧化硅层。 最后，将第二氧化硅层的一部分图案化以暴露第二导电层的一部分，从而在第二氧化物层中形成接触孔。

公开(公告)号：US6074952A

公开(公告)日：2000-06-13

申请号：US74341

申请日：1998-05-07

申请人： Hao-Chieh Liu ,  Erik S. Jeng ,  Bi-Ling Chen ,  Wan-Yih Lien

发明人： Hao-Chieh Liu ,  Erik S. Jeng ,  Bi-Ling Chen ,  Wan-Yih Lien

IPC分类号： H01L21/28 ,  H01L21/302 ,  H01L21/3065 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/768 ,  H01L21/8242 ,  H01L27/108 ,  H01L21/306

CPC分类号： H01L27/10894 ,  H01L21/31116 ,  H01L21/76816 ,  H01L27/10882

摘要： A method of forming a plurality of contact holes 70 in a semiconductor wafer uses a single step. The semiconductor wafer includes a dielectric layer 69 overlying a silicon substrate 51, a silicon nitride layer 67a, and a silicon oxynitride layer 63c. First, a photoresist 68 layer is developed on the dielectric layer. Prior to forming the dielectric layer, the silicon oxynitride layer is formed overlying a first conductive layer, and the silicon nitride layer is formed overlying a second conductive layer. Second, an etching step is performed to etch through the silicon oxynitride layer, the silicon nitride layer, a portion of the dielectric layer above the silicon oxynitride layer, and the silicon nitride layer to expose the silicon substrate 51, the first conductive layer 63a, and the second conductive layer 67c. The etching recipe includes a first chemistry and a second chemistry. The first chemistry includes C.sub.2 F.sub.6, C.sub.4 F.sub.8, CH.sub.3 F, and Ar. The second chemistry is chosen from a group including O.sub.2, CO.sub.2, CO and any combination thereof. Thus, a plurality of contact holes is formed above the silicon substrate, the first conductive layer and the second conductive layer.

摘要翻译： 在半导体晶片中形成多个接触孔70的方法使用一个步骤。 半导体晶片包括覆盖硅衬底51的电介质层69，氮化硅层67a和氮氧化硅层63c。 首先，在电介质层上显影光致抗蚀剂68层。 在形成电介质层之前，形成氮氧化硅层，覆盖第一导电层，并且氮化硅层形成在第二导电层上。 其次，进行蚀刻步骤以蚀刻穿过氧氮化硅层，氮化硅层，氧氮化硅层上方的电介质层的一部分和氮化硅层，以暴露硅衬底51，第一导电层63a， 和第二导电层67c。 该蚀刻配方包括第一化学和第二化学。 第一种化学性质包括C2F6，C4F8，CH3F和Ar。 第二化学选自包括O 2，CO 2，CO及其任何组合的组。 因此，在硅衬底，第一导电层和第二导电层上形成多个接触孔。

公开(公告)号：US5956594A

公开(公告)日：1999-09-21

申请号：US184345

申请日：1998-11-02

申请人： Fu-Liang Yang ,  Bi-Ling Chen ,  Erik S. Jeng

发明人： Fu-Liang Yang ,  Bi-Ling Chen ,  Erik S. Jeng

IPC分类号： H01L21/02 ,  H01L21/768 ,  H01L21/8242 ,  H01L21/20

CPC分类号： H01L27/10894 ,  H01L21/76895 ,  H01L28/60 ,  H01L27/10852 ,  H01L27/10888

摘要： A method for creating a DRAM device, featuring the simultaneous formation of a capacitor plate, used for a stacked capacitor structure, and the formation of a metal contact structure, and of a word line contact structure, has been developed. The process features the deposition of a barrier layer, and an overlying tungsten layer, on a storage node electrode, and with the deposition also completely filling a metal contact hole, and a word line hole. A patterning procedure, using an anisotropic RIE procedure, removes unwanted regions of tungsten and barrier layer, resulting in a capacitor plate, a metal contact structure, and a word line structure, all comprised of tungsten and the barrier layers, and all formed via one deposition procedure, and patterned using one RIE procedure.

摘要翻译： 已经开发了用于产生用于层叠电容器结构的电容器板的同时形成以及金属接触结构的形成以及字线接触结构的DRAM器件的制造方法。 该方法的特征在于在存储节点电极上沉积阻挡层和覆盖的钨层，并且沉积也完全填充金属接触孔和字线孔。 使用各向异性RIE程序的图案化步骤去除钨和阻挡层的不需要的区域，导致电容器板，金属接触结构和字线结构，全部由钨和阻挡层组成，并且都通过一个 沉积程序，并使用一个RIE程序进行图案化。

公开(公告)号：US06476488B1

公开(公告)日：2002-11-05

申请号：US09696086

申请日：2000-10-26

申请人： Erik S. Jeng ,  Bi-Ling Chen ,  Chien-Sheng Hsieh

发明人： Erik S. Jeng ,  Bi-Ling Chen ,  Chien-Sheng Hsieh

IPC分类号： H01L2348

CPC分类号： H01L27/10855 ,  H01L21/76895 ,  H01L21/76897 ,  H01L27/10888 ,  H01L27/10894

摘要： A method for making a novel structure having borderless and self-aligned polysilicon and metal contact landing plugs for multilevel interconnections on integrated circuits is achieved. An etch-stop layer and a planar insulating layer are formed over the devices on a substrate. Contact openings are etched in the insulating layer to the etch-stop layer and the etch-stop layer is removed over the N− contact areas. An N+ doped polysilicon layer is deposited, and second contact openings are etched in the polysilicon and insulating layers over N+ and P+ contacts on the substrate to the etch-stop layer. The etch-stop layer is selectively removed and a conducting barrier layer and a metal layer are deposited having a second etch-stop layer on the surface. The layers are patterned to form interconnecting lines and concurrently to form polysilicon landing plugs to the N− contacts, while forming metal landing plugs to the N+ and P+ contacts. Via holes can now be etched in a second insulating layer over and to the landing plugs. The polysilicon landing plugs to the N− contacts reduce current leakage, while the metal contacts to the N+ and P+ contacts reduce the contact resistance (Rc). The landing plugs protect the substrate contacts from damage during via hole etch and reduce the aspect ratio for making more reliable contacts.

摘要翻译： 实现了一种在集成电路上制造具有无边界和自对准多晶硅和用于多层互连的金属接触层塞的新型结构的方法。 在衬底上的器件上形成蚀刻停止层和平面绝缘层。 在绝缘层中蚀刻接触开口到蚀刻停止层，并且在N-接触区域上去除蚀刻停止层。 沉积N +掺杂的多晶硅层，并且第二接触开口在多晶硅中被蚀刻，并且在基板上的N +和P +接触上的绝缘层蚀刻到蚀刻停止层。 选择性地去除蚀刻停止层，并且在表面上沉积具有第二蚀刻停止层的导电阻挡层和金属层。 这些层被图案化以形成互连线并且同时形成到N触点的多晶硅着陆塞，同时向N +和P +接触形成金属着陆塞。 通孔现在可以在第二绝缘层上蚀刻到着陆塞上。 到N-接触点的多晶硅降落塞可以减少电流泄漏，而与N +和P +触点的金属接触会降低接触电阻（Rc）。 着陆插头可保护基板触点免受通孔蚀刻过程中的损坏，并降低纵横比，以提供更可靠的触点。

公开(公告)号：US06184081B2

公开(公告)日：2001-02-06

申请号：US09414807

申请日：1999-10-08

申请人： Erik S. Jeng ,  Bi-Ling Chen ,  Wei-Ray Lin ,  Yu-Chun Ho ,  Ming-Hong Kuo

发明人： Erik S. Jeng ,  Bi-Ling Chen ,  Wei-Ray Lin ,  Yu-Chun Ho ,  Ming-Hong Kuo

IPC分类号： H01L21336

CPC分类号： H01L27/10894 ,  H01L21/76805 ,  H01L21/76831 ,  H01L27/10811 ,  H01L27/10852 ,  H01L27/10888 ,  H01L28/60

摘要： A process for fabricating a DRAM capacitor structure, in which the capacitor upper plate structure is defined during the formation of bit line contact hole opening, and substrate contact hole opening procedure, eliminating the need for a specific upper plate, photolithographic masking procedure, has been developed. The process features isolating a polysilicon upper plate structure, during an isotropic RIE cycle, also creating an undercut polysilicon region, in the contact holes, which are opened simultaneously during the upper plate definition. Subsequent silicon nitride spacers, on the sides of the contact holes, provides insulation between the polysilicon upper plate structure, and bit line, and substrate contact plug structures, now located in the contact holes. The undercut polysilicon regions, allow the formation of thicker silicon nitride spacers, to be formed in this undercut region.

摘要翻译： 一种用于制造DRAM电容器结构的方法，其中在形成位线接触孔开口期间限定电容器上板结构和衬底接触孔打开程序，消除了对特定上板的需要，光刻掩模程序 发达。 在各向同性RIE循环期间隔离多晶硅上板结构的工艺特征还在上板定义期间同时打开的接触孔中产生底切多晶硅区域。 在接触孔的侧面上的随后的氮化硅间隔件提供多晶硅上板结构和位线之间的绝缘以及现在位于接触孔中的衬底接触插塞结构。 底切多晶硅区域允许在该底切区域中形成更厚的氮化硅间隔物。

公开(公告)号：US06239011B1

公开(公告)日：2001-05-29

申请号：US09089557

申请日：1998-06-03

申请人： Bi-Ling Chen ,  Erik S. Jeng

发明人： Bi-Ling Chen ,  Erik S. Jeng

IPC分类号： H01L21306

CPC分类号： H01L21/02063 ,  H01L21/31116 ,  H01L21/76897

摘要： The practice of forming self-aligned contacts (SACs) in MOSFETs using a silicon nitride gate sidewall and a silicon nitride gate cap has found wide acceptance, particularly in the manufacture of DRAMs, where bitline contacts are formed between two adjacent wordlines, each having a nitride sidewall. The contact etch requires a an RIE etch having a high oxide/nitride selectivity. In order to etch SACs having widths of less than 0.35 microns at their base, such as are encountered in high density DRAMs, special steps must be taken to prevent polymer bridging across the opening which leaves residual insulative material at the base of the contact. The problem is further complicated when the insulative layer through which the opening is formed comprises a silicate glass such as BPSG over a silicon oxide layer. The invention discloses the use of an etchant gas mixture containing octafluorocyclobutane and CH3F in combination with a small but critical concentration of oxygen to etch the SAC opening cleanly and without deleterious erosion of silicon nitride sidewall insulation. The added oxygen prevents polymer bridging across the narrow portion of the SAC.

摘要翻译： 在使用氮化硅栅极侧壁和氮化硅栅极帽的MOSFET中形成自对准触点（SAC）的做法已经被广泛接受，特别是在DRAM的制造中，其中在两个相邻字线之间形成位线触点，每个具有 氮化物侧壁。 接触蚀刻需要具有高氧化物/氮化物选择性的RIE蚀刻。 为了在其底部蚀刻具有小于0.35微米的宽度的SAC，例如在高密度DRAM中遇到的，必须采取特殊步骤以防止聚合物桥接穿过开口，从而在接触的基部留下残留的绝缘材料。 当形成开口的绝缘层在氧化硅层上包含诸如BPSG的硅酸盐玻璃时，问题更加复杂。 本发明公开了含有八氟环丁烷和CH 3 F的蚀刻剂气体混合物与小但临界浓度的氧的组合在蚀刻SAC开口并且没有氮化硅侧壁绝缘的有害侵蚀的用途。 添加的氧阻止聚合物桥接跨越SAC的窄部分。

公开(公告)号：US06245656B1

公开(公告)日：2001-06-12

申请号：US09435512

申请日：1999-11-08

申请人： Bi-Ling Chen ,  Erik S. Jeng ,  Shih-Ming Chang

发明人： Bi-Ling Chen ,  Erik S. Jeng ,  Shih-Ming Chang

IPC分类号： H01L214763

CPC分类号： H01L21/76816 ,  H01L21/31116 ,  H01L21/31138 ,  H01L21/31144 ,  Y10S438/952

摘要： The present invention relates to a method for overcming problems of amplified exposure light interference from shrinked devices and difficulties of photolithographic and etching process control due to multi-level contacts. The present invention combines reflective lights from multiple levels into one single light and reduces interference of reflective lights by introducing a reflective coating and an anti-reflective coating of SiON/Ti or SiON/TiN/Ti which further serve as an etching hard mask for avoiding overetching. The process windows are expanded. Semiconductor devices can be further shrunk and production yields an be improved.

摘要翻译： 本发明涉及一种用于过滤来自收缩装置的放大的曝光光干涉的问题的方法以及由于多层接触导致的光刻和蚀刻工艺控制的困难。 本发明将来自多层的反射光组合成一个单一的光，并通过引入SiON / Ti或SiON / TiN / Ti的反射涂层和抗反射涂层来减少反射光的干扰，SiON / Ti或SiON / TiN / Ti进一步用作蚀刻硬掩模以避免 过蚀刻 进程窗口展开。 半导体器件可以进一步收缩并且产量得到改善。

公开(公告)号：US6159839A

公开(公告)日：2000-12-12

申请号：US247977

申请日：1999-02-11

申请人： Erik S. Jeng ,  Bi-Ling Chen ,  Chien-Sheng Hsieh

发明人： Erik S. Jeng ,  Bi-Ling Chen ,  Chien-Sheng Hsieh

IPC分类号： H01L21/60 ,  H01L21/768 ,  H01L21/8242 ,  H01L21/4763

CPC分类号： H01L27/10855 ,  H01L21/76895 ,  H01L21/76897 ,  H01L27/10888 ,  H01L27/10894

摘要： A method for making a novel structure having borderless and self-aligned polysilicon and metal contact landing plugs for multilevel interconnections on integrated circuits is achieved. An etch-stop layer and a planar insulating layer are formed over the devices on a substrate. Contact openings are etched in the insulating layer to the etch-stop layer and the etch-stop layer is removed over the N.sup.- contact areas. An N.sup.+ doped polysilicon layer is deposited, and second contact openings are etched in the polysilicon and insulating layers over N.sup.+ and P.sup.+ contacts on the substrate to the etch-stop layer. The etch-stop layer is selectively removed and a conducting barrier layer and a metal layer are deposited having a second etch-stop layer on the surface. The layers are patterned to form interconnecting lines and concurrently to form polysilicon landing plugs to the N.sup.- contacts, while forming metal landing plugs to the N.sup.+ and P.sup.+ contacts. Via holes can now be etched in a second insulating layer over and to the landing plugs. The polysilicon landing plugs to the N.sup.- contacts reduce current leakage, while the metal contacts to the N.sup.+ and P.sup.+ contacts reduce the contact resistance (Rc). The landing plugs protect the substrate contacts from damage during via hole etch and reduce the aspect ratio for making more reliable contacts.