公开(公告)号：US08264896B2

公开(公告)日：2012-09-11

申请号：US12183767

申请日：2008-07-31

申请人： Bikas Maiti ,  Lawrence N. Herr ,  Rajesh R. Kini ,  Tam M. Tran

发明人： Bikas Maiti ,  Lawrence N. Herr ,  Rajesh R. Kini ,  Tam M. Tran

IPC分类号： G11C7/00 ,  G11C5/14

CPC分类号： G11C7/02 ,  G11C11/419

摘要： An integrated circuit comprises a plurality of memory cells and an array supply voltage control circuit. The plurality of memory cells are organized in rows and columns. A row comprises a word line and all of the memory cells coupled to the word line. A column comprises a bit line pair and all of the memory cells coupled to the bit line pair. The array supply voltage control circuit is coupled to the plurality of memory cells. The array supply voltage control circuit is for receiving a power supply voltage and for providing a reduced power supply voltage to memory cells of a selected column during a write operation in response to a voltage differential on the bit line pair of the selected column.

摘要翻译： 集成电路包括多个存储单元和阵列电源电压控制电路。 多个存储单元以行和列组织。 行包括字线和耦合到字线的所有存储器单元。 列包括位线对和耦合到位线对的所有存储器单元。 阵列电源电压控制电路耦合到多个存储单元。 阵列电源电压控制电路用于接收电源电压，并且在写操作期间响应于所选列的位线对上的电压差，向所选列的存储单元提供降低的电源电压。

公开(公告)号：US20100027360A1

公开(公告)日：2010-02-04

申请号：US12183767

申请日：2008-07-31

申请人： BIKAS MAITI ,  Lawrence N. Herr ,  Rajesh R. Kini ,  Tam M. Tran

发明人： BIKAS MAITI ,  Lawrence N. Herr ,  Rajesh R. Kini ,  Tam M. Tran

IPC分类号： G11C7/00 ,  G11C5/14

CPC分类号： G11C7/02 ,  G11C11/419

摘要： An integrated circuit comprises a plurality of memory cells and an array supply voltage control circuit. The plurality of memory cells are organized in rows and columns. A row comprises a word line and all of the memory cells coupled to the word line. A column comprises a bit line pair and all of the memory cells coupled to the bit line pair. The array supply voltage control circuit is coupled to the plurality of memory cells. The array supply voltage control circuit is for receiving a power supply voltage and for providing a reduced power supply voltage to memory cells of a selected column during a write operation in response to a voltage differential on the bit line pair of the selected column.

摘要翻译： 集成电路包括多个存储单元和阵列电源电压控制电路。 多个存储单元以行和列组织。 行包括字线和耦合到字线的所有存储器单元。 列包括位线对和耦合到位线对的所有存储器单元。 阵列电源电压控制电路耦合到多个存储单元。 阵列电源电压控制电路用于接收电源电压，并且在写操作期间响应于所选列的位线对上的电压差，向所选列的存储单元提供降低的电源电压。

公开(公告)号：US06956398B1

公开(公告)日：2005-10-18

申请号：US10806624

申请日：2004-03-23

申请人： Hugh Mair ,  Luan A. Dang ,  Xiaowei Deng ,  George B. Jamison ,  Tam M. Tran ,  Shyh-Horng Yang ,  David B. Scott

发明人： Hugh Mair ,  Luan A. Dang ,  Xiaowei Deng ,  George B. Jamison ,  Tam M. Tran ,  Shyh-Horng Yang ,  David B. Scott

IPC分类号： H03K17/16 ,  H03K19/00 ,  H03K19/003

CPC分类号： H03K19/00361 ,  H03K19/0016

摘要： The method for powering down a circuit for a data retention mode includes: changing a supply voltage node from an active power voltage level to an inactive power level; coupling a source of a P channel device to the supply voltage node; providing a retaining power supply voltage level to a back gate of the P channel device; changing a drain voltage of the P channel device to a reference voltage level, wherein the reference voltage level is different from the retaining power supply voltage level; and changing a gate voltage of the P channel device to the reference voltage level.

摘要翻译： 用于为数据保持模式断电的方法包括：将电源电压节点从有功功率电压电平改变为无功功率电平; 将P沟道器件的源极耦合到电源电压节点; 向P通道装置的后门提供保持电源电压电平; 将P沟道器件的漏极电压改变到参考电压电平，其中所述参考电压电平不同于所述保持电源电压电平; 并将P沟道器件的栅极电压改变到参考电压电平。

公开(公告)号：US06731564B1

公开(公告)日：2004-05-04

申请号：US10391006

申请日：2003-03-18

申请人： Tam M. Tran ,  George B. Jamison ,  Bryan D. Sheffield ,  David J. Toops ,  Vikas K. Agrawal

发明人： Tam M. Tran ,  George B. Jamison ,  Bryan D. Sheffield ,  David J. Toops ,  Vikas K. Agrawal

IPC分类号： G11C700

CPC分类号： G11C7/12 ,  G11C2207/002 ,  G11C2207/005 ,  G11C2207/2227

摘要： According to one embodiment of the invention, a memory circuit operable to assume a standby mode is provided. A memory circuit includes a transistor comprising a gate and a bulk. The bulk is at a retention voltage level. The memory circuit also includes a first node and a second node that are coupled to each other by the transistor. The first node is operable to assume a higher voltage level than the second node in response to an initiation of the standby mode. The memory circuit also includes a third node coupled to the gate of the transistor. The third node is operable to assume a voltage approximately equal to the retention voltage in response to an initiation of the standby mode. The transistor is operable to reduce any direct current flow between the first node and the second node in response to a rise in voltage at the third node to a voltage approximately equal to the retention voltage.

摘要翻译： 根据本发明的一个实施例，提供了可操作以呈现待机模式的存储器电路。 存储电路包括一个包括一个门和一个体的晶体管。 体积处于保持电压水平。 存储器电路还包括由晶体管彼此耦合的第一节点和第二节点。 响应于待机模式的启动，第一节点可操作以承担比第二节点更高的电压电平。 存储器电路还包括耦合到晶体管的栅极的第三节点。 第三节点可操作以响应于待机模式的启动而呈现大致等于保持电压的电压。 晶体管可操作以响应于第三节点处的电压升高到大约等于保持电压的电压而减小第一节点和第二节点之间的任何直流电流。