公开(公告)号：US06956398B1

公开(公告)日：2005-10-18

申请号：US10806624

申请日：2004-03-23

申请人： Hugh Mair ,  Luan A. Dang ,  Xiaowei Deng ,  George B. Jamison ,  Tam M. Tran ,  Shyh-Horng Yang ,  David B. Scott

发明人： Hugh Mair ,  Luan A. Dang ,  Xiaowei Deng ,  George B. Jamison ,  Tam M. Tran ,  Shyh-Horng Yang ,  David B. Scott

IPC分类号： H03K17/16 ,  H03K19/00 ,  H03K19/003

CPC分类号： H03K19/00361 ,  H03K19/0016

摘要： The method for powering down a circuit for a data retention mode includes: changing a supply voltage node from an active power voltage level to an inactive power level; coupling a source of a P channel device to the supply voltage node; providing a retaining power supply voltage level to a back gate of the P channel device; changing a drain voltage of the P channel device to a reference voltage level, wherein the reference voltage level is different from the retaining power supply voltage level; and changing a gate voltage of the P channel device to the reference voltage level.

摘要翻译： 用于为数据保持模式断电的方法包括：将电源电压节点从有功功率电压电平改变为无功功率电平; 将P沟道器件的源极耦合到电源电压节点; 向P通道装置的后门提供保持电源电压电平; 将P沟道器件的漏极电压改变到参考电压电平，其中所述参考电压电平不同于所述保持电源电压电平; 并将P沟道器件的栅极电压改变到参考电压电平。

公开(公告)号：US20050212554A1

公开(公告)日：2005-09-29

申请号：US10806624

申请日：2004-03-23

申请人： Hugh Mair ,  Luan Dang ,  Xiaowei Deng ,  George Jamison ,  Tam Tran ,  Shyh-Horng Yang ,  David Scott

发明人： Hugh Mair ,  Luan Dang ,  Xiaowei Deng ,  George Jamison ,  Tam Tran ,  Shyh-Horng Yang ,  David Scott

IPC分类号： H03K17/16 ,  H03K19/00 ,  H03K19/003

CPC分类号： H03K19/00361 ,  H03K19/0016

摘要： The method for powering down a circuit for a data retention mode includes: changing a supply voltage node from an active power voltage level to an inactive power level; coupling a source of a P channel device to the supply voltage node; providing a retaining power supply voltage level to a back gate of the P channel device; changing a drain voltage of the P channel device to a reference voltage level, wherein the reference voltage level is different from the retaining power supply voltage level; and changing a gate voltage of the P channel device to the reference voltage level.

摘要翻译： 用于为数据保持模式断电的方法包括：将电源电压节点从有功功率电压电平改变为无功功率电平; 将P沟道器件的源极耦合到电源电压节点; 向P通道装置的后门提供保持电源电压电平; 将P沟道器件的漏极电压改变到参考电压电平，其中所述参考电压电平不同于所述保持电源电压电平; 并将P沟道器件的栅极电压改变到参考电压电平。

公开(公告)号：US07384839B2

公开(公告)日：2008-06-10

申请号：US11239626

申请日：2005-09-29

申请人： Shyh-Horng Yang ,  Kayvan Sadra ,  Theodore W. Houston

发明人： Shyh-Horng Yang ,  Kayvan Sadra ,  Theodore W. Houston

IPC分类号： H01L21/8238

CPC分类号： H01L27/1104 ,  H01L21/26586 ,  H01L27/0207 ,  H01L27/11 ,  H01L29/1045 ,  H01L29/66659

摘要： A method of fabricating an SRAM cell with reduced leakage is disclosed. The method comprises fabricating asymmetrical transistors in the SRAM cell. The transistors are asymmetrical in a manner that reduces the drain leakage current of the transistors. The fabrication of asymmetrical pass transistors comprises forming a dielectric region on a surface of a substrate having a first conductivity type. A gate region having a length and a width is formed on the dielectric region. Source and drain extension regions having a second conductivity type are formed in the substrate on opposite sides of the gate region. A first pocket impurity region having a first concentration and the first conductivity type is formed adjacent the source. A second pocket impurity region having a second concentration and the first conductivity type may be formed adjacent the drain. If formed, the second concentration is smaller than the first concentration, reducing the gate induced drain leakage current.

摘要翻译： 公开了一种制造具有减少泄漏的SRAM单元的方法。 该方法包括在SRAM单元中制造不对称晶体管。 晶体管以不减小晶体管的漏极漏电流的方式是不对称的。 不对称传输晶体管的制造包括在具有第一导电类型的衬底的表面上形成电介质区域。 在电介质区域上形成具有长度和宽度的栅极区域。 具有第二导电类型的源极和漏极延伸区域形成在栅极区域的相对侧上的衬底中。 在源附近形成具有第一浓度和第一导电类型的第一杂质杂质区。 可以在漏极附近形成具有第二浓度和第一导电类型的第二袋杂质区域。 如果形成，则第二浓度小于第一浓度，减小了栅极引起的漏极漏电流。

公开(公告)号：US07692217B2

公开(公告)日：2010-04-06

申请号：US11948172

申请日：2007-11-30

申请人： Henry Litzmann Edwards ,  Hisashi Shichijo ,  Tathagata Chatterjee ,  Shyh-Horng Yang ,  Lance Stanford Robertson

发明人： Henry Litzmann Edwards ,  Hisashi Shichijo ,  Tathagata Chatterjee ,  Shyh-Horng Yang ,  Lance Stanford Robertson

IPC分类号： H01L27/148

CPC分类号： H01L21/823892 ,  H01L21/823814 ,  H01L27/0928

摘要： One embodiment of the invention relates to an integrated circuit. The integrated circuit includes a first matched transistor comprising: a first source region, a first drain region formed within a first drain well extension, and a first gate electrode having lateral edges about which the first source region and first drain region are laterally disposed. The integrated circuit also includes a second matched transistor comprising: a second source region, a second drain region formed within a second drain well extension, and a second gate electrode having lateral edges about which the second source region and second drain region are laterally disposed. Analog circuitry is associated with the first and second matched transistors, which analog circuitry utilizes a matching characteristic of the first and second matched transistors to facilitate analog functionality. Other devices, methods, and systems are also disclosed.

摘要翻译： 本发明的一个实施例涉及集成电路。 集成电路包括第一匹配晶体管，包括：第一源极区域，形成在第一漏极阱延伸​​部内的第一漏极区域和具有横向边缘的第一栅极电极，第一源极区域和第一漏极区域围绕第一源极区域横向设置。 集成电路还包括第二匹配晶体管，其包括：第二源极区域，形成在第二漏极阱延伸​​部内的第二漏极区域和具有横向边缘的第二栅极电极，第二源极区域和第二漏极区域围绕第二源极区域横向设置。 模拟电路与第一和第二匹配晶体管相关联，该模拟电路利用第一和第二匹配晶体管的匹配特性来促进模拟功能。 还公开了其他装置，方法和系统。

公开(公告)号：US20100065925A1

公开(公告)日：2010-03-18

申请号：US12424170

申请日：2009-04-15

申请人： Huan-Tsung Huang ,  Shyh-Horng Yang ,  Yuri Masuoka ,  Ken-Ichi Goto

发明人： Huan-Tsung Huang ,  Shyh-Horng Yang ,  Yuri Masuoka ,  Ken-Ichi Goto

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/7833 ,  H01L21/28088 ,  H01L29/42376 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/6656 ,  H01L29/6659

摘要： The present disclosure provides a semiconductor device. The semiconductor device includes a semiconductor substrate having a source region and a drain region, defining a first dimension from the source to drain; and a gate stack disposed on the semiconductor substrate and partially interposed between the source region and the drain region. The gate stack includes a high k dielectric layer disposed on the semiconductor substrate; a first metal feature disposed on the high k dielectric layer, the first metal gate feature having a first work function and defining a second dimension parallel with the first dimension; and a second metal feature having a second work function different from the first work function and defining a third dimension parallel with the first dimension, the third dimension being less than the second dimension.

摘要翻译： 本发明提供一种半导体器件。 半导体器件包括具有源极区和漏极区的半导体衬底，限定从源极到漏极的第一维度; 以及设置在所述半导体衬底上并部分插入在所述源极区域和所述漏极区域之间的栅极堆叠。 栅极堆叠包括设置在半导体衬底上的高k电介质层; 第一金属特征设置在高k电介质层上，第一金属栅极特征具有第一功函数并限定与第一维平行的第二维度; 以及具有不同于所述第一功函数的第二功函数并且限定与所述第一尺寸平行的第三尺寸的第二金属特征，所述第三尺寸小于所述第二尺寸。

公开(公告)号：US08679926B2

公开(公告)日：2014-03-25

申请号：US13232154

申请日：2011-09-14

申请人： Huan-Tsung Huang ,  Shyh-Horng Yang ,  Yuri Masuoka ,  Ken-Ichi Goto

发明人： Huan-Tsung Huang ,  Shyh-Horng Yang ,  Yuri Masuoka ,  Ken-Ichi Goto

IPC分类号： H01L21/336

CPC分类号： H01L29/7833 ,  H01L21/28088 ,  H01L29/42376 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/6656 ,  H01L29/6659

摘要： The present disclosure provides a semiconductor device. The semiconductor device includes a semiconductor substrate having a source region and a drain region, defining a first dimension from the source to drain; and a gate stack disposed on the semiconductor substrate and partially interposed between the source region and the drain region. The gate stack includes a high k dielectric layer disposed on the semiconductor substrate; a first metal feature disposed on the high k dielectric layer, the first metal gate feature having a first work function and defining a second dimension parallel with the first dimension; and a second metal feature having a second work function different from the first work function and defining a third dimension parallel with the first dimension, the third dimension being less than the second dimension.

摘要翻译： 本发明提供一种半导体器件。 半导体器件包括具有源极区和漏极区的半导体衬底，限定从源极到漏极的第一维度; 以及设置在所述半导体衬底上并部分插入在所述源极区域和所述漏极区域之间的栅极堆叠。 栅极堆叠包括设置在半导体衬底上的高k电介质层; 第一金属特征设置在高k电介质层上，第一金属栅极特征具有第一功函数并限定与第一维平行的第二维度; 以及具有不同于所述第一功函数的第二功函数并且限定与所述第一尺寸平行的第三尺寸的第二金属特征，所述第三尺寸小于所述第二尺寸。

公开(公告)号：US20120261768A1

公开(公告)日：2012-10-18

申请号：US13478839

申请日：2012-05-23

申请人： Theodore W. Houston ,  Shyh-Horng Yang ,  Kayvan Sadra

发明人： Theodore W. Houston ,  Shyh-Horng Yang ,  Kayvan Sadra

IPC分类号： H01L27/11

CPC分类号： H01L27/1104 ,  H01L21/26586 ,  H01L27/11 ,  H01L29/1045 ,  H01L29/1083 ,  H01L29/665 ,  H01L29/66659

摘要： A method of controlling gate induced drain leakage current of a transistor is disclosed. The method includes forming a dielectric region (516) on a surface of a substrate having a first concentration of a first conductivity type (P-well). A gate region (500) having a length and a width is formed on the dielectric region. Source (512) and drain (504) regions having a second conductivity type (N+) are formed in the substrate on opposite sides of the gate region. A first impurity region (508) having the first conductivity type (P+) is formed adjacent the source. The first impurity region has a second concentration greater than the first concentration.

摘要翻译： 公开了一种控制晶体管的栅感应漏极漏电流的方法。 该方法包括在具有第一导电类型（P阱）的第一浓度的衬底的表面上形成电介质区域（516）。 在电介质区域上形成具有长度和宽度的栅极区域（500）。 在栅极区域的相对侧的衬底中形成具有第二导电类型（N +）的源极（512）和漏极（504）区域。 在源附近形成具有第一导电类型（P +）的第一杂质区（508）。 第一杂质区域具有大于第一浓度的第二浓度。

公开(公告)号：US08258587B2

公开(公告)日：2012-09-04

申请号：US12561358

申请日：2009-09-17

申请人： Yuri Masuoka ,  Shyh-Horng Yang ,  Peng-Soon Lim

发明人： Yuri Masuoka ,  Shyh-Horng Yang ,  Peng-Soon Lim

IPC分类号： H01L29/792 ,  H01L21/336

CPC分类号： H01L21/28114 ,  H01L21/28088 ,  H01L29/42376 ,  H01L29/4966 ,  H01L29/7833

摘要： The present disclosure provides a method for making a semiconductor device having metal gate stacks. The method includes forming a high k dielectric material layer on a semiconductor substrate; forming a metal gate layer on the high k dielectric material layer; forming a top gate layer on the metal gate layer; patterning the top gate layer, the metal gate layer and the high k dielectric material layer to form a gate stack; performing an etching process to selectively recess the metal gate layer; and forming a gate spacer on sidewalls of the gate stack.

摘要翻译： 本公开提供了制造具有金属栅极叠层的半导体器件的方法。 该方法包括在半导体衬底上形成高k电介质材料层; 在高k电介质材料层上形成金属栅极层; 在所述金属栅极层上形成顶栅层; 图案化顶栅层，金属栅极层和高k电介质材料层以形成栅叠层; 执行蚀刻工艺以选择性地凹陷金属栅极层; 以及在所述栅极堆叠的侧壁上形成栅极间隔物。

公开(公告)号：US20120003804A1

公开(公告)日：2012-01-05

申请号：US13232154

申请日：2011-09-14

申请人： Huan-Tsung Huang ,  Shyh-Horng Yang ,  Yuri Masuoka ,  Ken-Ichi Goto

发明人： Huan-Tsung Huang ,  Shyh-Horng Yang ,  Yuri Masuoka ,  Ken-Ichi Goto

IPC分类号： H01L21/336 ,  H01L21/28

CPC分类号： H01L29/7833 ,  H01L21/28088 ,  H01L29/42376 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/6656 ,  H01L29/6659

摘要： The present disclosure provides a semiconductor device. The semiconductor device includes a semiconductor substrate having a source region and a drain region, defining a first dimension from the source to drain; and a gate stack disposed on the semiconductor substrate and partially interposed between the source region and the drain region. The gate stack includes a high k dielectric layer disposed on the semiconductor substrate; a first metal feature disposed on the high k dielectric layer, the first metal gate feature having a first work function and defining a second dimension parallel with the first dimension; and a second metal feature having a second work function different from the first work function and defining a third dimension parallel with the first dimension, the third dimension being less than the second dimension.

摘要翻译： 本发明提供一种半导体器件。 半导体器件包括具有源极区和漏极区的半导体衬底，限定从源极到漏极的第一维度; 以及设置在所述半导体衬底上并部分插入在所述源极区域和所述漏极区域之间的栅极堆叠。 栅极堆叠包括设置在半导体衬底上的高k电介质层; 第一金属特征设置在高k电介质层上，第一金属栅极特征具有第一功函数并限定与第一维平行的第二维度; 以及具有不同于所述第一功函数的第二功函数并且限定与所述第一尺寸平行的第三尺寸的第二金属特征，所述第三尺寸小于所述第二尺寸。

公开(公告)号：US08030718B2

公开(公告)日：2011-10-04

申请号：US12424170

申请日：2009-04-15

申请人： Huan-Tsung Huang ,  Shyh-Horng Yang ,  Yuri Masuoka ,  Ken-Ichi Goto

发明人： Huan-Tsung Huang ,  Shyh-Horng Yang ,  Yuri Masuoka ,  Ken-Ichi Goto

IPC分类号： H01L29/76

CPC分类号： H01L29/7833 ,  H01L21/28088 ,  H01L29/42376 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/6656 ,  H01L29/6659

摘要： The present disclosure provides a semiconductor device. The semiconductor device includes a semiconductor substrate having a source region and a drain region, defining a first dimension from the source to drain; and a gate stack disposed on the semiconductor substrate and partially interposed between the source region and the drain region. The gate stack includes a high k dielectric layer disposed on the semiconductor substrate; a first metal feature disposed on the high k dielectric layer, the first metal gate feature having a first work function and defining a second dimension parallel with the first dimension; and a second metal feature having a second work function different from the first work function and defining a third dimension parallel with the first dimension, the third dimension being less than the second dimension.

摘要翻译： 本发明提供一种半导体器件。 半导体器件包括具有源极区和漏极区的半导体衬底，限定从源极到漏极的第一维度; 以及设置在所述半导体衬底上并部分插入在所述源极区域和所述漏极区域之间的栅极堆叠。 栅极堆叠包括设置在半导体衬底上的高k电介质层; 第一金属特征设置在高k电介质层上，第一金属栅极特征具有第一功函数并限定与第一维平行的第二维度; 以及具有不同于所述第一功函数的第二功函数并且限定与所述第一尺寸平行的第三尺寸的第二金属特征，所述第三尺寸小于所述第二尺寸。