公开(公告)号：US06956398B1

公开(公告)日：2005-10-18

申请号：US10806624

申请日：2004-03-23

申请人： Hugh Mair ,  Luan A. Dang ,  Xiaowei Deng ,  George B. Jamison ,  Tam M. Tran ,  Shyh-Horng Yang ,  David B. Scott

发明人： Hugh Mair ,  Luan A. Dang ,  Xiaowei Deng ,  George B. Jamison ,  Tam M. Tran ,  Shyh-Horng Yang ,  David B. Scott

IPC分类号： H03K17/16 ,  H03K19/00 ,  H03K19/003

CPC分类号： H03K19/00361 ,  H03K19/0016

摘要： The method for powering down a circuit for a data retention mode includes: changing a supply voltage node from an active power voltage level to an inactive power level; coupling a source of a P channel device to the supply voltage node; providing a retaining power supply voltage level to a back gate of the P channel device; changing a drain voltage of the P channel device to a reference voltage level, wherein the reference voltage level is different from the retaining power supply voltage level; and changing a gate voltage of the P channel device to the reference voltage level.

摘要翻译： 用于为数据保持模式断电的方法包括：将电源电压节点从有功功率电压电平改变为无功功率电平; 将P沟道器件的源极耦合到电源电压节点; 向P通道装置的后门提供保持电源电压电平; 将P沟道器件的漏极电压改变到参考电压电平，其中所述参考电压电平不同于所述保持电源电压电平; 并将P沟道器件的栅极电压改变到参考电压电平。

公开(公告)号：US06731564B1

公开(公告)日：2004-05-04

申请号：US10391006

申请日：2003-03-18

申请人： Tam M. Tran ,  George B. Jamison ,  Bryan D. Sheffield ,  David J. Toops ,  Vikas K. Agrawal

发明人： Tam M. Tran ,  George B. Jamison ,  Bryan D. Sheffield ,  David J. Toops ,  Vikas K. Agrawal

IPC分类号： G11C700

CPC分类号： G11C7/12 ,  G11C2207/002 ,  G11C2207/005 ,  G11C2207/2227

摘要： According to one embodiment of the invention, a memory circuit operable to assume a standby mode is provided. A memory circuit includes a transistor comprising a gate and a bulk. The bulk is at a retention voltage level. The memory circuit also includes a first node and a second node that are coupled to each other by the transistor. The first node is operable to assume a higher voltage level than the second node in response to an initiation of the standby mode. The memory circuit also includes a third node coupled to the gate of the transistor. The third node is operable to assume a voltage approximately equal to the retention voltage in response to an initiation of the standby mode. The transistor is operable to reduce any direct current flow between the first node and the second node in response to a rise in voltage at the third node to a voltage approximately equal to the retention voltage.

摘要翻译： 根据本发明的一个实施例，提供了可操作以呈现待机模式的存储器电路。 存储电路包括一个包括一个门和一个体的晶体管。 体积处于保持电压水平。 存储器电路还包括由晶体管彼此耦合的第一节点和第二节点。 响应于待机模式的启动，第一节点可操作以承担比第二节点更高的电压电平。 存储器电路还包括耦合到晶体管的栅极的第三节点。 第三节点可操作以响应于待机模式的启动而呈现大致等于保持电压的电压。 晶体管可操作以响应于第三节点处的电压升高到大约等于保持电压的电压而减小第一节点和第二节点之间的任何直流电流。

公开(公告)号：US06201757B1

公开(公告)日：2001-03-13

申请号：US09376042

申请日：1999-08-17

申请人： M. Dwayne Ward ,  Vikas Agrawal ,  George B. Jamison

发明人： M. Dwayne Ward ,  Vikas Agrawal ,  George B. Jamison

IPC分类号： G11C800

CPC分类号： G11C7/14 ,  G11C7/1072 ,  G11C7/22 ,  G11C11/419

摘要： A memory timing architecture which very accurately tracks the read and write timing of a memory over a wide range of array sizes, with separate read and write timing circuits. The read reset circuitry uses a plurality of dummy cells to gauge the time necessary to complete the read operation, while the write reset uses a single dummy cell to gauge the time necessary to complete the write operation. These circuits provide for a more accurately-timed feedback signal, which allows for increased speed while at the same time reducing power consumption and heat buildup.

摘要翻译： 一种存储器定时架构，其使用单独的读取和写入定时电路非常精确地跟踪存储器在宽范围的阵列尺寸上的读取和写入定时。 读取复位电路使用多个虚拟单元来测量完成读取操作所需的时间，而写入复位使用单个虚拟单元来测量完成写入操作所需的时间。 这些电路提供更准确的定时反馈信号，这允许增加速度，同时降低功耗和积热。

公开(公告)号：US06414900B1

公开(公告)日：2002-07-02

申请号：US09998824

申请日：2001-12-03

申请人： Stephen W. Spriggs ,  George B. Jamison

发明人： Stephen W. Spriggs ,  George B. Jamison

IPC分类号： G11C800

CPC分类号： G11C8/00 ,  G11C8/10

摘要： A memory device (10) includes a memory array (12) having storage units (14) arranged in a plurality of rows (16). A row decoder (18) receives address information and determines which of the plurality of rows (16) to enable. According to the determined row (16), a row selector (20) drives the storage units (14) associated with the determined row (16) to provide their outputs onto respective bitlines (34) for identification by a bitline sensor (22). If the received address information indicates an out of range address that does not identify any of the plurality of rows (16) of the memory array (12), an out of range decoder (24) provides such determination to drive an out of range selector (26) to enable storage units (30) arranged in a single row (32) of a bitline driver (28). Outputs from the storage units (30) are applied to the respective bitlines (34) during an out of range address occurrence to prevent the bitlines (34) from being placed in an undesirable floating state.

摘要翻译： 存储器件（10）包括具有排列成多行（16）的存储单元（14）的存储器阵列（12）。 行解码器（18）接收地址信息并确定多个行（16）中的哪一行能够使能。 根据确定的行（16），行选择器（20）驱动与所确定的行（16）相关联的存储单元（14），以将它们的输出提供到相应的位线（34）上以供位线传感器（22）识别。 如果接收到的地址信息指示不识别存储器阵列（12）的多个行（16）中的任何一个的超出范围地址，则超出范围解码器（24）提供这样的确定以驱动超出范围选择器 （26），以使得能够布置在位线驱动器（28）的单行（32）中的存储单元（30）。 在超出范围地址发生期间，来自存储单元（30）的输出被施加到相应的位线（34），以防止位线（34）被置于不期望的浮动状态。

公开(公告)号：US6005794A

公开(公告)日：1999-12-21

申请号：US106034

申请日：1998-06-26

申请人： Bryan D. Sheffield ,  George B. Jamison ,  Stephen Wayne Spriggs

发明人： Bryan D. Sheffield ,  George B. Jamison ,  Stephen Wayne Spriggs

IPC分类号： G11C8/16 ,  G11C11/419 ,  G11C11/00

CPC分类号： G11C11/419 ,  G11C8/16

摘要： The write port circuits of a static memory cell includes a first conditional conduction path between a first output of the latch and ground active if and only if both a word line input and a write data true bit line input receive active signals. The write port circuit includes a second conditional conduction path between a second output of the latch and ground active if and only if both the word line and a write data complement bit line receive active signals. The first and second conditional conduction paths may be formed by a series connection of the source-drain paths of two transistors. In each conditional conduction path the gate of a first transistor receives a corresponding column signal and the gate of a second transistor is connected to the word line. The first and second transistors for each conduction path may be N-channel MOS transistors formed in a single N-type region. The first and second transistors forming the conditional conduction paths may be in either order. The word line transistors may bee shared between bit line transistors of a single memory cell or of memory cells in plural contiguous adjacent columns. The memory cells may include a plurality of write ports with this inventive write port circuit used for each write port.

摘要翻译： 静态存储单元的写入端口电路包括当且仅当字线输入和写入数据真位线输入都接收到有效信号时，锁存器的第一输出和接地有效信号之间的第一条件传导路径。 写入端口电路包括在锁存器的第二输出和接地有效之间的第二条件传导路径，当且仅当字线和写入数据补码位线都接收到有效信号时。 第一和第二条件导通路径可以由两个晶体管的源极 - 漏极路径的串联连接形成。 在每个条件导通路径中，第一晶体管的栅极接收对应的列信号，并且第二晶体管的栅极连接到字线。 用于每个导电路径的第一和第二晶体管可以是形成在单个N型区域中的N沟道MOS晶体管。 形成条件传导路径的第一和第二晶体管可以是任何一个顺序。 字线晶体管可以在单个存储器单元的位线晶体管或多个相邻相邻列中的存储器单元之间共享。 存储器单元可以包括多个写入端口，其具有用于每个写入端口的本发明的写入端口电路。

公开(公告)号：US07152187B2

公开(公告)日：2006-12-19

申请号：US10723377

申请日：2003-11-26

申请人： Tam Minh Tran ,  George B. Jamison

发明人： Tam Minh Tran ,  George B. Jamison

IPC分类号： G06F11/00

CPC分类号： G11C29/802

摘要： A low power E-fuse repair methodology substantially removes system latency during memory and/or E-fuse farm module power-down in a device that employs E-fuse farm technology. The method maintains power to the repair registers and minimal control logic in the memories, while all other circuitry can be either placed in a low power data retention mode, or completely powered off. There is no need to rescan the repair data from the E-fuse farm after one or more memories are powered back up. This provides dynamic power savings since there is no longer any need to idle the system to reload repair data. Since the E-fuse farm can be powered down after initial system power-up and repair data is loaded into the memories, there is also a significant leakage power savings.

摘要翻译： 在采用电熔丝农场技术的设备中，低功率电熔丝修复方法可显着消除存储器和/或E-fuse农场模块断电期间的系统延迟。 该方法维持修复寄存器的电源和存储器中的最小控制逻辑，而所有其他电路可以放置在低功率数据保持模式或完全断电。 一个或多个存储器上电后，不需要重新扫描电源保险丝座的修复数据。 这样可以节省动力，因为不再需要空闲系统来重新加载修复数据。 由于电源熔断器场在初始系统上电后可以关闭电源，并将数据修复到存储器中，所以还可以节省大量的泄漏功率。

公开(公告)号：US06965261B2

公开(公告)日：2005-11-15

申请号：US10712198

申请日：2003-11-13

申请人： Tam Minh Tran ,  George B. Jamison

发明人： Tam Minh Tran ,  George B. Jamison

IPC分类号： H03K3/3562 ,  H03K3/012 ,  H03K3/037 ,  H03K3/289

CPC分类号： H03K3/012 ,  H03K3/0375

摘要： An embodiment of a ultra low-power data retention latch circuit involves a slave latch SL that concurrently latches the same data that is loaded into a main circuit (such as a main latch ML) during normal operation. When the circuit enters a low power (data retention) mode, power (VCC) to the main latch ML is removed and the slave latch SL retains the most recent data (retained data SA, SA-). When power is being restored to the main latch ML, the slave latch's retained data SA, SA- is quickly restored to the main latch ML through what constitute Set and Reset inputs SAR, SAR- of the ML. This arrangement ensures that data restoration is much quicker than conventional arrangements that require the output data path DATA- to be stabilized before power is re-applied to the main latch. Further, there is no need to wait for power to the ML to be stable before restoring data from the SL to the ML, providing an increase in data restoration speed over conventional data retention latches. Using retained data SA, SA- (as mirrored in SAR, SAR-) to control the Set and Reset inputs prevents data contention in the main latch ML. Moreover, compared to known arrangements, the arrangement provides minimal loading on the DATA, DATA- output paths (driving only N7, N8), thus not compromising speed on the data path (DATAIN . . . DATA/DATA-) through the main latch during normal operation.

摘要翻译： 超低功率数据保持锁存电路的一个实施例涉及从锁存器SL，其在正常操作期间同时锁存加载到主电路（例如主锁存器ML）中的相同数据。 当电路进入低功耗（数据保持）模式时，主锁存器ML的电源（VCC）被去除，从锁存器SL保留最近的数据（保留数据SA，SA-）。 当电源恢复到主锁存器ML时，从锁存器的保留数据SA，SA-通过构成ML的设置和复位输入SAR，SAR-快速恢复到主锁存器ML。 这种布置确保了数据恢复比传统的布置要快得多，需要在将电源重新施加到主锁存器之前使输出数据路径DATA-稳定。 此外，在将数据从SL恢复到ML之前，不需要等待ML的电源稳定，从而提供比常规数据保持锁存器更高的数据恢复速度。 使用保留数据SA，SA-（如SAR，SAR-中镜像）来控制设置和复位输入防止主锁存器ML中的数据争用。 此外，与已知布置相比，该布置在DATA，DATA-输出路径（仅驱动N7，N8）上提供最小的负载，因此不会损害数据路径（DATAIN ... DATA / DATA-）上的速度 主闩锁正常运行。