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公开(公告)号：US06731564B1
公开(公告)日：2004-05-04
申请号：US10391006
申请日：2003-03-18
IPC分类号： G11C700
CPC分类号： G11C7/12 , G11C2207/002 , G11C2207/005 , G11C2207/2227
摘要： According to one embodiment of the invention, a memory circuit operable to assume a standby mode is provided. A memory circuit includes a transistor comprising a gate and a bulk. The bulk is at a retention voltage level. The memory circuit also includes a first node and a second node that are coupled to each other by the transistor. The first node is operable to assume a higher voltage level than the second node in response to an initiation of the standby mode. The memory circuit also includes a third node coupled to the gate of the transistor. The third node is operable to assume a voltage approximately equal to the retention voltage in response to an initiation of the standby mode. The transistor is operable to reduce any direct current flow between the first node and the second node in response to a rise in voltage at the third node to a voltage approximately equal to the retention voltage.
摘要翻译： 根据本发明的一个实施例，提供了可操作以呈现待机模式的存储器电路。 存储电路包括一个包括一个门和一个体的晶体管。 体积处于保持电压水平。 存储器电路还包括由晶体管彼此耦合的第一节点和第二节点。 响应于待机模式的启动，第一节点可操作以承担比第二节点更高的电压电平。 存储器电路还包括耦合到晶体管的栅极的第三节点。 第三节点可操作以响应于待机模式的启动而呈现大致等于保持电压的电压。 晶体管可操作以响应于第三节点处的电压升高到大约等于保持电压的电压而减小第一节点和第二节点之间的任何直流电流。
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公开(公告)号：US07234034B2
公开(公告)日：2007-06-19
申请号：US10663597
申请日：2003-09-16
IPC分类号： G06F13/00
CPC分类号： G11C7/1063 , G11C7/1051 , G11C7/22
摘要： A self-clocking memory device comprises a memory array, a memory input circuit, and a memory control circuit. The memory input circuit is operable to receive an input clock signal and generate a memory operation initiation signal in response thereto, while the memory control circuit is operable to receive the memory operation initiation signal and generate one or more control signals to initiate a memory operation in response thereto. The memory control circuit is further operable to identify completion of the memory operation and generate a cycle ready strobe signal in response thereto. The memory input circuit receives the cycle ready strobe signal as an input and generates a next memory operation initiation signal in response thereto for initiation of a next memory operation.
摘要翻译： 自定时存储器件包括存储器阵列，存储器输入电路和存储器控制电路。 存储器输入电路可操作以接收输入时钟信号并响应于此产生存储器操作启动信号，而存储器控制电路可操作以接收存储器操作启动信号并产生一个或多个控制信号以启动存储器操作 回应。 存储器控制电路还可操作以识别存储器操作的完成并响应于此产生周期就绪选通信号。 存储器输入电路接收周期就绪选通信号作为输入，并且响应于此产生下一个存储器操作启动信号以启动下一个存储器操作。
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3.发明授权Method of operating a memory at high speed using a cycle ready status output signal 有权使用循环就绪状态输出信号高速运行存储器的方法公开(公告)号：US07200730B2
公开(公告)日：2007-04-03
申请号：US10663144
申请日：2003-09-16
IPC分类号： G06F13/00
CPC分类号： G11C7/1063 , G11C7/04 , G11C7/1051 , G11C7/22
摘要： A self-clocking memory device comprises a memory array, a memory input circuit, and a memory control circuit. The memory input circuit is operable to receive an input clock signal and generate a memory operation initiation signal in response thereto, while the memory control circuit is operable to receive the memory operation initiation signal and generate one or more control signals to initiate a memory operation in response thereto. The memory control circuit is further operable to identify completion of the memory operation and generate a cycle ready strobe signal in response thereto. The memory input circuit receives the cycle ready strobe signal as an input and generates a next memory operation initiation signal in response thereto for initiation of a next memory operation.
摘要翻译： 自定时存储器件包括存储器阵列，存储器输入电路和存储器控制电路。 存储器输入电路可操作以接收输入时钟信号并响应于此产生存储器操作启动信号，而存储器控制电路可操作以接收存储器操作启动信号并产生一个或多个控制信号以启动存储器操作 回应。 存储器控制电路还可操作以识别存储器操作的完成并响应于此产生周期就绪选通信号。 存储器输入电路接收周期就绪选通信号作为输入，并且响应于此产生下一个存储器操作启动信号以启动下一个存储器操作。
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公开(公告)号：US06956789B2
公开(公告)日：2005-10-18
申请号：US10663575
申请日：2003-09-16
CPC分类号： G11C7/1063 , G11C7/1051 , G11C7/22 , G11C7/222 , G11C2207/2281
摘要： A self-clocking memory device comprises a memory array, a memory input circuit, and a memory control circuit. The memory input circuit is operable to receive an input clock signal and generate a memory operation initiation signal in response thereto, while the memory control circuit is operable to receive the memory operation initiation signal and generate one or more control signals to initiate a memory operation in response thereto. The memory control circuit is further operable to identify completion of the memory operation and generate a cycle ready strobe signal in response thereto. The memory input circuit receives the cycle ready strobe signal as an input and generates a next memory operation initiation signal in response thereto for initiation of a next memory operation.
摘要翻译： 自定时存储器件包括存储器阵列，存储器输入电路和存储器控制电路。 存储器输入电路可操作以接收输入时钟信号并响应于此产生存储器操作启动信号，而存储器控制电路可操作以接收存储器操作启动信号并产生一个或多个控制信号以启动存储器操作 回应。 存储器控制电路还可操作以识别存储器操作的完成并响应于此产生周期就绪选通信号。 存储器输入电路接收周期就绪选通信号作为输入，并且响应于此产生下一个存储器操作启动信号以启动下一个存储器操作。
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公开(公告)号：US6005794A
公开(公告)日：1999-12-21
申请号：US106034
申请日：1998-06-26
IPC分类号： G11C8/16 , G11C11/419 , G11C11/00
CPC分类号： G11C11/419 , G11C8/16
摘要： The write port circuits of a static memory cell includes a first conditional conduction path between a first output of the latch and ground active if and only if both a word line input and a write data true bit line input receive active signals. The write port circuit includes a second conditional conduction path between a second output of the latch and ground active if and only if both the word line and a write data complement bit line receive active signals. The first and second conditional conduction paths may be formed by a series connection of the source-drain paths of two transistors. In each conditional conduction path the gate of a first transistor receives a corresponding column signal and the gate of a second transistor is connected to the word line. The first and second transistors for each conduction path may be N-channel MOS transistors formed in a single N-type region. The first and second transistors forming the conditional conduction paths may be in either order. The word line transistors may bee shared between bit line transistors of a single memory cell or of memory cells in plural contiguous adjacent columns. The memory cells may include a plurality of write ports with this inventive write port circuit used for each write port.
摘要翻译： 静态存储单元的写入端口电路包括当且仅当字线输入和写入数据真位线输入都接收到有效信号时，锁存器的第一输出和接地有效信号之间的第一条件传导路径。 写入端口电路包括在锁存器的第二输出和接地有效之间的第二条件传导路径，当且仅当字线和写入数据补码位线都接收到有效信号时。 第一和第二条件导通路径可以由两个晶体管的源极 - 漏极路径的串联连接形成。 在每个条件导通路径中，第一晶体管的栅极接收对应的列信号，并且第二晶体管的栅极连接到字线。 用于每个导电路径的第一和第二晶体管可以是形成在单个N型区域中的N沟道MOS晶体管。 形成条件传导路径的第一和第二晶体管可以是任何一个顺序。 字线晶体管可以在单个存储器单元的位线晶体管或多个相邻相邻列中的存储器单元之间共享。 存储器单元可以包括多个写入端口，其具有用于每个写入端口的本发明的写入端口电路。
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6.发明申请公开(公告)号：US20080158928A1
公开(公告)日：2008-07-03
申请号：US11617771
申请日：2006-12-29
CPC分类号： G11C15/00
摘要： A technique that provides width expansion of two CAMs of varying widths by combining match results from two CAMs by integrating the two CAMs. In one embodiment, a synchronizer circuit triggers the operation of an External Priority Encoder module which can be used to cascade two CAMs to form a wider CAM. When the External Priority Encoder module is used with the CAM, the External Priority Encoder module will receive MATCH signals and control signals from individual CAMs residing on either side, and will be triggered by the last arriving signal between two ports associated with two CAMs. In case one of the ports is disabled the External Priority Encoder module relies totally on the control signal from the other port for operation. The synchronizer circuit has the ability to handle mismatches between the CAMs as well as differentiating valid and invalid combinations between the CAMs.
摘要翻译： 通过组合两个CAM，通过组合来自两个CAM的匹配结果来提供两个不同宽度的CAM的宽度扩展的技术。 在一个实施例中，同步器电路触发外部优先级编码器模块的操作，外部优先级编码器模块可用于级联两个CAM以形成较宽的CAM。 当外部优先级编码器模块与CAM一起使用时，外部优先级编码器模块将接收来自驻留在任一侧的各个CAM的MATCH信号和控制信号，并且将由与两个CAM相关联的两个端口之间的最后到达信号触发。 如果一个端口被禁用，则外部优先级编码器模块完全依赖来自另一端口的控制信号进行操作。 同步器电路具有处理CAM之间的不匹配以及区分CAM之间的有效和无效组合的能力。
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公开(公告)号：US07012846B2
公开(公告)日：2006-03-14
申请号：US10768098
申请日：2004-02-02
IPC分类号： G11C7/00
CPC分类号： G11C7/227 , G11C7/067 , G11C2207/063
摘要： A sense amplifier which senses whether current is present on a bit line, and generates one logical value if current is present and another logical value if current is not present. As the sense amplifier can be implemented to generate such logical values with a current signal of low strength, memory arrays with correspondingly low drive strength can be implemented. As a result, memory systems which consume minimal power and having high density can be provided. In addition, as the sense amplifiers can operate without any reference signals, the implementation of sense amplifiers may be simplified.
摘要翻译： 感测放大器，其感测电流是否存在于位线上，并且如果存在电流并且如果电流不存在则产生一个逻辑值，并且如果电流不存在则产生另一个逻辑值。 由于可以实现读出放大器以用低强度的电流信号生成这样的逻辑值，所以可以实现具有相应低的驱动强度的存储器阵列。 结果，可以提供消耗最小功率并具有高密度的存储器系统。 此外，由于读出放大器可以在没有参考信号的情况下工作，因此可以简化读出放大器的实现。
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8.发明授权
公开(公告)号：US6088288A
公开(公告)日：2000-07-11
申请号：US405480
申请日：1999-09-24
CPC分类号： G11C5/14 , G11C7/1078
摘要： A method of reducing power supply current transients in a memory array caused by a simultaneous change in logic state of numerous CMOS digital circuits during a memory write cycle. Write driver enable signals (ENT, ENC) and bitcell enable signals (WBC1-WBC24) are sequentially delayed in time during the write cycle through use of the propagation delay of inverters (INV1-INV24-7). The sequential time delay reduces the number of circuits that are simultaneously changing logic state at any given time during the write cycle. The power supply current transient is transformed from a single, large change in current to a series of smaller changes displaced in time from each other during the write cycle. The ground bounce of the power supply network attributed to the current transient is significantly reduced, such change in ground potential being directly related to the magnitude of the current transient and its rate of change with respect to time.
摘要翻译： 一种在存储器写入周期期间由许多CMOS数字电路的逻辑状态的同时改变引起的减少存储器阵列中的电源电流瞬变的方法。 通过使用逆变器（INV1-INV24-7）的传播延迟，写入周期期间写入驱动器使能信号（ENT，ENC）和位单元使能信号（WBC1-WBC24）在时间上顺序延迟。 顺序时间延迟减少了在写周期期间的任何给定时间同时改变逻辑状态的电路的数量。 在写周期期间，电源电流瞬变从单个大的电流变化转变为在时间上彼此偏移的一系列较小的变化。 归因于电流瞬变的电源网络的地面反弹明显减少，这种地电位的变化与当前瞬态的幅度及其相对于时间的变化率直接相关。
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公开(公告)号：US07120082B2
公开(公告)日：2006-10-10
申请号：US10945725
申请日：2004-09-21
IPC分类号： G11C8/00
CPC分类号： G11C8/08 , G11C11/417
摘要： The present invention provides a system for reducing row periphery power consumption in a semiconductor memory device, particularly during sleep mode operation. A memory device (100) according to the present invention has a row (106) of memory cells and driver circuitry (102) preceding the row of memory cells. The present invention provides an intervention circuit (114) instantiated within the driver circuitry proximal to the row of memory cells. The intervention circuit is operated to hold the row of memory cells at a desired state, while the driver circuitry (108, 110) preceding the intervention circuit is powered down.
摘要翻译： 本发明提供了一种用于减少半导体存储器件中的行周边功耗的系统，特别是在睡眠模式操作期间。 根据本发明的存储器件（100）在存储器单元行之前具有一行（106）存储单元和驱动器电路（102）。 本发明提供了一种在靠近该行存储器单元的驱动器电路内实例化的介入电路（114）。 在介入电路之前的驱动器电路（108,110）掉电的同时，介入电路被操作以将该行存储器单元保持在期望的状态。
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公开(公告)号：US06876594B2
公开(公告)日：2005-04-05
申请号：US10739520
申请日：2003-12-19
申请人： Roger C. Griesmer , Robert L. Pitts , Bryan D. Sheffield , Kun-His Li , Mark J. Jensen , Vinod J. Menezes
发明人： Roger C. Griesmer , Robert L. Pitts , Bryan D. Sheffield , Kun-His Li , Mark J. Jensen , Vinod J. Menezes
IPC分类号： H01L21/82 , G11C8/20 , G11C11/56 , G11C17/16 , G11C17/18 , G11C29/02 , H03K19/177 , G11C7/00
CPC分类号： G11C29/02 , G11C8/20 , G11C11/56 , G11C17/16 , G11C17/18 , G11C29/027 , G11C2216/26
摘要： An integrated circuit (IC). The integrated circuit comprises an array (14) of data cells arranged in a plurality of rows and a plurality of columns. Each of the data cells comprises an electrically programmable fuse (40), and each electrically programmable fuse comprises a current path for providing a first digital state when the current path is left intact and for providing a second digital state when the current path is destroyed. Each row of the plurality of rows comprises at least one cell reserved for providing a protection indicator for the row, wherein the protection indicator is selected from a set consisting of read protection and write protection. The integrated circuit also comprises control circuitry (12) for selectively destroying the programmable fuse in selected ones of the data cells in a programmation mode. The integrated circuit also comprises control circuitry (12) for reading selected ones of the data cells in a read mode.
摘要翻译： 集成电路（IC）。 集成电路包括布置成多行和多列的数据单元的阵列（14）。 每个数据单元包括电可编程熔丝（40），并且每个电可编程熔丝包括电流路径，用于当当前路径保持原状时提供第一数字状态，并且当当前路径被破坏时提供第二数字状态。 多行中的每行包括至少一个保留用于为该行提供保护指示符的单元，其中保护指示符是从由读保护和写保护组成的集合中选择的。 集成电路还包括用于以编程模式选择性地破坏所选数据单元中的可编程熔丝的控制电路（12）。 集成电路还包括用于在读取模式下读取所选数据单元的控制电路（12）。
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