公开(公告)号：US06277729B1

公开(公告)日：2001-08-21

申请号：US09042855

申请日：1998-03-17

Applicant: Bing-Chang Wu ,  Cheng-Hui Chung

Inventor： Bing-Chang Wu ,  Cheng-Hui Chung

IPC: H01L214763

CPC classification number: H01L21/76856 ,  H01L21/76843

Abstract: A method for improving the fabrication of a transistor barrier layer that utilizes an ion bombardment treatment after the formation of the titanium nitride layer for reducing contact resistance and preventing tungsten plug stringer generation. The method comprises the step of patterning a transistor to form vias, and then depositing a titanium/titanium nitride layer over the transistor surface using a collimator sputtering method. Next, an ion bombardment treatment is carried out, and then a rapid thermal processing operation is performed. Finally, tungsten is deposited to fill the vias follow by a planarization. This invention is able to lower contact resistance because titanium in the titanium layer will not react with gaseous ammonia or nitrogen in the reacting chamber to form a high resistance titanium nitride layer during rapid thermal processing operation. In the meantime, no short-circuiting stringers leading from the tungsten plug to the titanium nitride layer below are formed because no cracks are formed in a titanium nitride layer that has been subjected to a stress reducing ion bombardment treatment.

Abstract translation: 一种用于改善在形成用于降低接触电阻并防止钨插塞纵梁产生的氮化钛层形成之后利用离子轰击处理的晶体管势垒层的制造方法。 该方法包括图案化晶体管以形成通孔，然后使用准直器溅射方法在晶体管表面上沉积钛/氮化钛层的步骤。 接下来，进行离子轰击处理，然后进行快速热处理操作。 最后，通过平坦化沉积钨来填充通孔。 本发明能够降低接触电阻，因为在快速热处理操作期间，钛层中的钛不会与反应室中的气态氨或氮反应形成高电阻氮化钛层。 同时，由于在经过减压离子轰击处理的氮化钛层中没有形成裂纹，因此形成了从钨丝塞向下方的氮化钛层的短路桁条。

公开(公告)号：US07274108B2

公开(公告)日：2007-09-25

申请号：US10904540

申请日：2004-11-15

Applicant: Bing-Chang Wu

Inventor： Bing-Chang Wu

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC classification number: H01L24/05 ,  H01L23/5223 ,  H01L24/06 ,  H01L2224/02166 ,  H01L2224/05093 ,  H01L2224/05553 ,  H01L2224/05624 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/05042 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/00014

Abstract: A semiconductor chip capable of implementing wire bonding over active circuits (BOAC) is provided. The semiconductor chip includes a bonding pad structure, a metal-metal capacitor formed by at least a pair of metal electrodes on the same plane underneath the bonding pad structure, at least an interconnection metal layer, at least a via plug between the interconnection metal layer and the bonding pad structure, and an active circuit situated underneath the bonding pad structure on a semiconductor bottom.

Abstract translation: 提供了能够通过有源电路（BOAC）实现引线键合的半导体芯片。 所述半导体芯片包括接合焊盘结构，金属 - 金属电容器，其由至少一对金属电极在所述焊盘结构下方的同一平面上形成，至少互连金属层，所述互连金属层 和焊盘结构，以及位于半导体底部上的焊盘结构下方的有源电路。

公开(公告)号：US20060103031A1

公开(公告)日：2006-05-18

申请号：US10904540

申请日：2004-11-15

Applicant: Bing-Chang Wu

Inventor： Bing-Chang Wu

IPC: H01L23/48

CPC classification number: H01L24/05 ,  H01L23/5223 ,  H01L24/06 ,  H01L2224/02166 ,  H01L2224/05093 ,  H01L2224/05553 ,  H01L2224/05624 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/05042 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/00014

Abstract: A semiconductor chip capable of implementing wire bonding over active circuits (BOAC) is provided. The semiconductor chip includes a bonding pad structure, a metal-metal capacitor formed by at least a pair of metal electrodes on the same plane underneath the bonding pad structure, at least an interconnection metal layer, at least a via plug between the interconnection metal layer and the bonding pad structure, and an active circuit situated underneath the bonding pad structure on a semiconductor bottom.

Abstract translation: 提供了能够通过有源电路（BOAC）实现引线键合的半导体芯片。 所述半导体芯片包括接合焊盘结构，金属 - 金属电容器，其由至少一对金属电极在所述焊盘结构下方的同一平面上形成，至少互连金属层，至少所述互连金属层 和焊盘结构，以及位于半导体底部上的焊盘结构下方的有源电路。

公开(公告)号：US20060030082A1

公开(公告)日：2006-02-09

申请号：US11250820

申请日：2005-10-13

Applicant: Bing-Chang Wu

Inventor： Bing-Chang Wu

IPC: H01L21/82

CPC classification number: H01L24/02 ,  H01L23/5256 ,  H01L23/5258 ,  H01L2924/01005 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01033 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/00

Abstract: A semiconductor device comprising a substrate with an integrated circuit structure and a patterned metallic layer thereon is provided. The patterned metallic layer includes a first pattern and a second pattern. The first pattern has a thickness different from the second pattern. Since the first pattern and the second pattern on the substrate each has a thickness optimized for their respective use, performance of the semiconductor device is improved.

公开(公告)号：US06482739B2

公开(公告)日：2002-11-19

申请号：US09790163

申请日：2001-02-21

Applicant: Bing-Chang Wu

Inventor： Bing-Chang Wu

IPC: H01L214763

CPC classification number: H01L29/66507 ,  H01L21/28518 ,  H01L29/4933

Abstract: This invention relates to a method for decreasing the resistivity of the gate and leaky junction of the source/drain, more particularly, to the method for forming a metal silicide layer at the gate region and the source/drain region by using two times in depositing metal layer. This condition will form a thicker metal silicide layer at the gate region to decrease the resistivity of the gate and will form a thinner metal silicide layer at the source/drain region to decrease defects in leaky junction at the source/drain region. At first, a semiconductor substrate is provided and a MOS is formed on the substrate and a shallow trench isolation is formed in the substrate. The MOS comprises a gate region, a source region, a drain region, and a spacer which is formed on the sidewall of the gate. The first metal layer is formed over the MOS and a oxide layer is formed over the first metal layer. Partial oxide layer is etched to show the first metal layer which is formed on the gate. The first metal layer which is on the gate is removed. The remained oxide is removed. The second metal layer is formed on the first metal layer. Then two times rapid thermal process are passed through and the salicide process is finished.

Abstract translation: 本发明涉及一种用于降低源极/漏极的栅极和漏极结的电阻率的方法，更具体地说，涉及通过使用两次沉积在栅极区域和源极/漏极区域形成金属硅化物层的方法 金属层。 该条件将在栅极区域形成较厚的金属硅化物层，以降低栅极的电阻率，并在源极/漏极区域形成较薄的金属硅化物层，以减少源极/漏极区域漏点的缺陷。 首先，提供半导体衬底并且在衬底上形成MOS，并在衬底中形成浅沟槽隔离。 MOS包括形成在栅极的侧壁上的栅极区域，源极区域，漏极区域和间隔物。 在MOS上形成第一金属层，在第一金属层上形成氧化物层。 蚀刻部分氧化物层以示出在栅极上形成的第一金属层。 去除栅极上的第一金属层。 剩余的氧化物被去除。 第二金属层形成在第一金属层上。 然后通过两次快速热处理，自杀处理完成。

公开(公告)号：US07372168B2

公开(公告)日：2008-05-13

申请号：US11379572

申请日：2006-04-21

Applicant: Bing-Chang Wu ,  Kun-Chih Wang ,  Mei-Ling Chao ,  Shiao-Shien Chen

Inventor： Bing-Chang Wu ,  Kun-Chih Wang ,  Mei-Ling Chao ,  Shiao-Shien Chen

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC classification number: H01L24/05 ,  H01L23/53228 ,  H01L2224/02166 ,  H01L2224/05093 ,  H01L2224/05095 ,  H01L2224/05624 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/05042 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/00014

Abstract: A semiconductor chip capable of implementing wire bonding over active circuits (BOAC) is provided. The semiconductor chip includes a bonding pad structure which includes a bondable metal pad, a top interconnection metal layer, a stress-buffering dielectric, and at least a first via plug between the bondable metal pad and the top interconnection metal layer. The semiconductor chip also includes at least an interconnection metal layer, at least a second via plug between the interconnection metal layer and the bonding pad structure, and an active circuit situated underneath the bonding pad structure on a semiconductor substrate.

Abstract translation: 提供了能够通过有源电路（BOAC）实现引线键合的半导体芯片。 该半导体芯片包括一个焊盘结构，该焊盘结构包括一个可粘合的金属焊盘，一个顶部互连金属层，一个应力缓冲电介质，以及至少一个可焊接的金属焊盘和顶部互连金属层之间的第一通孔塞。 半导体芯片还至少包括互连金属层，在互连金属层和焊盘结构之间的至少第二通孔插塞以及位于半导体衬底上的焊盘结构下方的有源电路。

公开(公告)号：US07208837B2

公开(公告)日：2007-04-24

申请号：US10907959

申请日：2005-04-22

Applicant: Kun-Chih Wang ,  Bing-Chang Wu

Inventor： Kun-Chih Wang ,  Bing-Chang Wu

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC classification number: H01L24/05 ,  H01L23/53238 ,  H01L2224/02166 ,  H01L2224/05093 ,  H01L2224/05095 ,  H01L2224/05624 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/05042 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/19041 ,  Y10T428/24917 ,  Y10T428/265 ,  H01L2924/00014

Abstract: A reinforced bonding pad structure includes a bondable metal layer defined on a stress-buffering dielectric layer, and an intermediate metal layer damascened in a first inter-metal dielectric (IMD) layer disposed under the stress-buffering dielectric layer. The intermediate metal layer is situated directly under the bondable metal layer and is electrically connected to the bondable metal layer with a plurality of via plugs integrated with the bondable metal layer. A metal frame is damascened in a second IMD layer under the first IMD layer. The metal frame is situated directly under the intermediate metal layer for counteracting mechanical stress exerted on the bondable metal layer during bonding, when the thickness of said stress-buffering dielectric layer is greater than 2000 angstroms, the damascened metal frame may be omitted. An active circuit portion including active circuit components of the integrated circuit is situated directly under the metal frame.

公开(公告)号：US06900541B1

公开(公告)日：2005-05-31

申请号：US10708109

申请日：2004-02-10

Applicant: Kun-Chih Wang ,  Bing-Chang Wu

Inventor： Kun-Chih Wang ,  Bing-Chang Wu

IPC: H01L23/485 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC classification number: H01L24/05 ,  H01L2224/02166 ,  H01L2224/05093 ,  H01L2224/05095 ,  H01L2224/05624 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/05042 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/19041

Abstract: An integrated circuit including a reinforced bonding pad structure is disclosed. The reinforced bonding pad structure includes a bondable metal layer defined on a stress-buffering dielectric layer, and an intermediate metal layer damascened in a first inter-metal dielectric (IMD) layer disposed under the stress-buffering dielectric layer. The intermediate metal layer is situated directly under the bondable metal layer and is electrically connected to the bondable metal layer with a plurality of via plugs integrated with the bondable metal layer. At least one metal frame is damascened in a second IMD layer under the first IMD layer. The metal frame is situated directly under the intermediate metal layer for counteracting mechanical stress exerted on the bondable metal layer during bonding. An active circuit portion including active circuit components of the integrated circuit is situated directly under the metal frame of the reinforced bonding pad structure.

Abstract translation: 公开了一种包括加固焊盘结构的集成电路。 强化焊盘结构包括限定在应力缓冲电介质层上的可粘合金属层和在应力缓冲介电层下设置的第一金属间电介质（IMD）层中的中间金属层。 中间金属层位于可接合的金属层的正下方，并且与可结合金属层电连接，多个通孔与可结合的金属层集成。 在第一IMD层下面的第二IMD层中至少一个金属框架被镶嵌。 金属框架位于中间金属层的正下方，用于抵抗在粘合期间施加在可粘合金属层上的机械应力。 包括集成电路的有源电路部件的有源电路部分位于加固焊盘结构的金属框架的正下方。

公开(公告)号：US06235566B1

公开(公告)日：2001-05-22

申请号：US09472131

申请日：1999-12-23

Applicant: Bing-Chang Wu

Inventor： Bing-Chang Wu

IPC: H01L218238

CPC classification number: H01L29/66507 ,  H01L21/28052 ,  H01L21/762 ,  H01L21/76224 ,  H01L29/6659

Abstract: A two-step silicidation process for fabricating a semiconductor device is disclosed. The method includes the following steps. Firstly, two trench isolation regions are formed in a semiconductor substrate. A gate oxide layer and a polysilicon layer and a barrier layer are formed. Patterning is carried out to etch portions of the barrier layer. The areas between the trench isolation regions and the gate region are respectively used as a source area and a drain area. First ions are implanted into the substrate. A dielectric layer is blanket formed and the dielectric layer is etched back to form dielectric spacer. The second ions are implanted into the substrate. The first silicide regions respectively are formed in the source area and the drain area. A poly-metal dielectric (PMD) layer is formed and is etched back. Finally, the second silicide region is formed on and in the polysilicon layer.

Abstract translation: 公开了用于制造半导体器件的两步硅化工艺。 该方法包括以下步骤。 首先，在半导体衬底中形成两个沟槽隔离区域。 形成栅极氧化层和多晶硅层以及阻挡层。 执行图案化以蚀刻阻挡层的部分。 沟槽隔离区域和栅极区域之间的区域分别用作源极区域和漏极区域。 将第一离子注入衬底。 电介质层被覆盖形成并且电介质层被回蚀以形成电介质间隔物。 将第二离子注入到衬底中。 第一硅化物区域分别形成在源极区域和漏极区域中。 形成多金属电介质（PMD）层并将其回蚀。 最后，在多晶硅层上形成第二硅化物区域。

公开(公告)号：US07250670B2

公开(公告)日：2007-07-31

申请号：US11162863

申请日：2005-09-27

Applicant: Chien-Li Kuo ,  Bing-Chang Wu ,  Jui-Meng Jao

Inventor： Chien-Li Kuo ,  Bing-Chang Wu ,  Jui-Meng Jao

IPC: H01L23/544

CPC classification number: H01L23/585 ,  H01L23/5283 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor structure is provided. The semiconductor structure is disposed on the scribe line of a wafer and is around the chip area of the wafer. The semiconductor structure includes a plurality of dielectric layers sequentially disposed on the scribe line and a plurality of metal patterns disposed in each dielectric layer. The metal patterns disposed in each dielectric layer extend to the next underlying dielectric layer.

Abstract translation: 提供半导体结构。 半导体结构设置在晶片的划线上并且在晶片的芯片区域周围。 半导体结构包括顺序地设置在划线上的多个电介质层和设置在每个电介质层中的多个金属图案。 设置在每个电介质层中的金属图案延伸到下一个下面的介电层。