公开(公告)号：US07365903B2

公开(公告)日：2008-04-29

申请号：US11601817

申请日：2006-11-20

申请人： Bo Hun Choi ,  Sang Soo Lee ,  Chang Bong Kim ,  Je Soo Ko

发明人： Bo Hun Choi ,  Sang Soo Lee ,  Chang Bong Kim ,  Je Soo Ko

IPC分类号： H01S3/00

CPC分类号： H01S3/1302 ,  H01S3/005 ,  H01S3/0064 ,  H01S3/0078 ,  H01S3/06758 ,  H01S3/1608 ,  H01S2301/04 ,  H04B10/294

摘要： Provided is an apparatus and method for all-optically controlling both a gain and a gain flattening. The apparatus includes: a first amplifier automatically controlling a gain of the apparatus through a feedback loop while amplifying a received optical signal; a fixed gain flattening unit receiving the amplified optical signal from the first amplifier and compensating for the gain according to a wavelength of the received optical signal; and a second amplifier automatically controlling the gain through a feedback loop while amplifying the optical signal input from the fixed gain flattening unit. Accordingly, even if the number of channels of an input WDM optical signal varies, both of a gain and a gain flattening can be all-optically controlled.

摘要翻译： 提供了一种用于全光控制增益和增益平坦化的装置和方法。 该装置包括：第一放大器，通过反馈回路自动控制装置的增益，同时放大接收到的光信号; 固定增益平坦化单元，从第一放大器接收放大的光信号，并根据所接收的光信号的波长补偿增益; 并且第二放大器通过反馈环路自动地控制增益，同时放大从固定增益平坦化单元输入的光信号。 因此，即使输入WDM光信号的信道数量变化，增益和增益平坦化也可以全光控制。

公开(公告)号：US07412173B2

公开(公告)日：2008-08-12

申请号：US10802762

申请日：2004-03-18

申请人： Dong Soo Lee ,  Man Seop Lee ,  Sang Soo Lee ,  Je Soo Ko

发明人： Dong Soo Lee ,  Man Seop Lee ,  Sang Soo Lee ,  Je Soo Ko

IPC分类号： H04B10/04

CPC分类号： H04B10/505 ,  H04B10/5051 ,  H04B10/508

摘要： An apparatus for generating a Carrier-Suppressed Return-to-Zero (CS-RZ) signal is disclosed. The apparatus includes a mixer, a Low Pass Filter (LPF), a driver amplifier and a single external modulator. The mixer generates a modulator input by mixing data with a half clock signal. The LPF band-limits the modulator input data into low frequency band data. The driver amplifier amplifies the modulator input data generated by the mixing of the mixer and the band-limiting of the LPF. The external modulator generates CS-RZ signal, in which the phases of adjacent pulses have been inverted, by applying bias voltage to the modulator input data to be placed at the null point of the transfer function of the external modulator.

摘要翻译： 公开了一种用于产生载波抑制归零（CS-RZ）信号的装置。 该装置包括混频器，低通滤波器（LPF），驱动放大器和单个外部调制器。 混频器通过将数据与半个时钟信号混合来产生调制器输入。 LPF频带将调制器输入数据限制为低频带数据。 驱动器放大器放大由混频器混频产生的调制器输入数据和LPF的带限制。 外部调制器通过向调制器输入数据施加偏置电压而产生CS-RZ信号，其中相邻脉冲的相位已被反相，以将其置于外部调制器的传递函数的零点。

公开(公告)号：US07515007B2

公开(公告)日：2009-04-07

申请号：US11441655

申请日：2006-05-26

申请人： Sang Kyu Lim ,  Sang Soo Lee ,  Hyun Woo Cho ,  Je Soo Ko

发明人： Sang Kyu Lim ,  Sang Soo Lee ,  Hyun Woo Cho ,  Je Soo Ko

IPC分类号： H03B5/30

CPC分类号： H03B9/148 ,  H01P1/20309

摘要： Provided are an integrated dielectric resonator filter and a clock extraction device using the integrated dielectric resonator filter. The integrated dielectric resonator filter includes: a microwave substrate; a disc type dielectric resonator installed on the microwave substrate and having predetermined diameter and height; an input and output transmission line installed on both sides of the disc type dielectric resonator to transmit input and output signals; and a metal cover enclosing the disc type dielectric resonator to form a predetermined volume, opened toward the input and output transmission line, and closed in an orthogonal direction to the input and output transmission line.

摘要翻译： 提供了一种集成介质谐振器滤波器和使用集成介质谐振滤波器的时钟提取装置。 集成介质谐振器滤波器包括：微波基板; 安装在微波基板上并具有预定直径和高度的盘型介质谐振器; 安装在盘式介质谐振器两侧的输入和输出传输线，以传输输入和输出信号; 以及包围盘状介质谐振器以形成预定体积的金属盖，朝向输入和输出传输线路开口，并且沿与输入和输出传输线正交的方向封闭。

公开(公告)号：US07624311B2

公开(公告)日：2009-11-24

申请号：US11947349

申请日：2007-11-29

申请人： Jong Yoon Shin ,  Hyun Jae Lee ,  Je Soo Ko

发明人： Jong Yoon Shin ,  Hyun Jae Lee ,  Je Soo Ko

IPC分类号： G06K5/04

CPC分类号： H04J3/1611 ,  H04L25/14

摘要： Provided are a method and an apparatus for converting an interface between high speed data having various capacities. The apparatus includes a data transmitting part and a data receiving part. The data transmitting part generates a deskew channel having respective timing data of a plurality of data transmitted from a first communicating device, and outputs the generated deskew channel together with the plurality of data to a second communicating device. The data receiving part compares the deskew channel transmitted from the second communicating device with the plurality of data to measure skew values of the data, aligns bits and bytes of the plurality of data using the skew values, and transmits the plurality of data to the first communicating device.

摘要翻译： 提供了一种用于转换具有各种容量的高速数据之间的接口的方法和装置。 该装置包括数据发送部分和数据接收部分。 数据发送部生成具有从第一通信装置发送的多个数据的各自的定时数据的歪斜通道，并将生成的歪斜通道与多个数据一起输出到第二通信装置。 数据接收部将从第二通信装置发送的歪斜通道与多个数据进行比较，以测量数据的偏斜值，使用偏斜值对准多个数据的比特和字节，并将多个数据发送到第一个 通讯设备

公开(公告)号：US20090150708A1

公开(公告)日：2009-06-11

申请号：US12316280

申请日：2008-12-11

申请人： Jongho Kim ,  Jong Yoon Shin ,  Je Soo Ko

发明人： Jongho Kim ,  Jong Yoon Shin ,  Je Soo Ko

IPC分类号： G06F11/00 ,  H04L29/04

CPC分类号： H04L25/14 ,  H03M9/00

摘要： The development of transmission technologies have resulted in a several tens Gbps optical transmission system. In the present invention, a low-speed FPGA receives a plurality of several Gbps signals according to a very high-speed parallel converting unit and the SFI-5, divides each of the plurality of several Gbps signals into a plurality of several hundreds (Mbps) parallel signals, and processes the plurality of several hundreds (Mbps) parallel signals in order to constitute an SFI-5 receiving end.

摘要翻译： 传输技术的发展已经导致了数十Gbps光传输系统。 在本发明中，低速FPGA根据非常高速的并行转换单元接收多个Gbps信号，并且SFI-5将多个Gbps信号中的每一个分成多个数百（Mbps） ）并行信号，并且处理多个数百个（Mbps）并行信号，以构成SFI-5接收端。

公开(公告)号：US20080313253A1

公开(公告)日：2008-12-18

申请号：US12051503

申请日：2008-03-19

申请人： Jong-Yoon Shin ,  Hanho Lee ,  Seungbeom Lee ,  Je Soo Ko

发明人： Jong-Yoon Shin ,  Hanho Lee ,  Seungbeom Lee ,  Je Soo Ko

IPC分类号： G06F11/08

CPC分类号： H03M13/1535 ,  H03M13/6575

摘要： Provided are an operation circuit for a modified Euclidean algorithm in a high-speed Reed-Solomon (RS) decoder and a method of implementing the modified Euclidean algorithm. Since a finite state machine (FSM) for generating a stop signal and an FSM for generating a control signal that controls a swap operation, a shift operation, and a polynomial operation for each basic cell of the modified Euclidean algorithm are used, an area-efficient RS decoder can be realized without using a conventional degree computation unit for comparing and calculating degrees.

摘要翻译： 提供了一种用于高速里德 - 所罗门（RS）解码器中的修改的欧几里德算法的操作电路和实现修改的欧几里德算法的方法。 由于使用用于产生停止信号的有限状态机（FSM）和用于产生控制交换操作的控制信号的FSM，所以使用修改的欧几里德算法的每个基本单元的移位操作和多项式操作， 可以在不使用用于比较和计算度的常规度计算单元的情况下实现高效的RS解码器。

公开(公告)号：US07330664B2

公开(公告)日：2008-02-12

申请号：US10860903

申请日：2004-06-03

申请人： Wangjoo Lee ,  Hyunwoo Cho ,  Ki Ho Han ,  Je Soo Ko

发明人： Wangjoo Lee ,  Hyunwoo Cho ,  Ki Ho Han ,  Je Soo Ko

IPC分类号： H04B10/04 ,  H04B10/00

CPC分类号： H04B10/505 ,  H04B10/541

摘要： The present invention relates to none return to zero (NRZ) modulation method. The NRZ optical modulation is performed by combining a clock signal and NRZ data at a sending end and signal distortion capable of being generated when the clock signal and the NRZ data are combined is optimized by controlling the magnitude and phase of the clock signal. At the receiving end, the clock signal is extracted by performing narrow band band-pass filtering of the detected optical signal transmitted from a transmitter and data is recovered using the clock signal. Therefore, a receiver structure for clock extraction is simpler, an error rate of data recovery is lower by clearly extracting the clock signal, and transmission distance of the optical signal is longer.

公开(公告)号：US07796621B2

公开(公告)日：2010-09-14

申请号：US12184468

申请日：2008-08-01

申请人： Seung Hwan Kim ,  Je Soo Ko

发明人： Seung Hwan Kim ,  Je Soo Ko

IPC分类号： H04W4/00 ,  H04L12/28 ,  H04L12/56 ,  H04J3/04

CPC分类号： H04L12/413

摘要： Provided is an apparatus for matching Gigabit Ethernet (GbE) signals to an Optical Transport Hierarchy (OTH). The apparatus real-time records a source address and input port information of GbE Ethernet frames in a memory, compares a destination address of the Ethernet frame which is a payload of a GFP frame with memory table information, searches an output port location of the GbE, and interreceives GbE frames and Generic Frame Procedure (GFP) frames by multiplexing/demultiplexing.

摘要翻译： 提供了一种用于将千兆以太网（GbE）信号与光传送层级（OTH）相匹配的装置。 该装置实时记录存储器中的GbE以太网帧的源地址和输入端口信息，将作为GFP帧的有效载荷的以太网帧的目的地地址与存储器表信息进行比较，搜索GbE的输出端口位置 ，并通过复用/解复用来互连GbE帧和通用帧过程（GFP）帧。

公开(公告)号：US07653092B2

公开(公告)日：2010-01-26

申请号：US11406105

申请日：2006-04-18

申请人： Joon Hak Bang ,  Hyun Woo Cho ,  Sang Kyu Lim ,  Wang Joo Lee ,  Je Soo Ko

发明人： Joon Hak Bang ,  Hyun Woo Cho ,  Sang Kyu Lim ,  Wang Joo Lee ,  Je Soo Ko

IPC分类号： H04J3/06 ,  H04J3/04

CPC分类号： H04J3/0685 ,  H04J3/047

摘要： Provided are a time-division data multiplexing/demultiplexing system and method capable of preventing errors in processing data signals which occur due to a phase difference between data signals and a multiplexing reference clock in a multiplexing process or a phase difference between a multiplexed data signal and a demultiplexing reference clock in a demultiplexing process. The time-division data multiplexing system includes: a phase adjusting unit which adjusts a phase of each of a plurality of data signals having different phases from one another for enabling the data signals to be time-division multiplexed when a plurality of values of the data signals indicate a stable state; and a multiplexer time-division multiplexing the phase adjusted data signals according to a multiplexing reference clock.

摘要翻译： 提供了一种时分数据复用/解复用系统和方法，其能够防止在复用处理中数据信号与多路复用基准时钟之间的相位差产生的数据信号的处理中的错误或多路复用数据信号与 解复用处理中的解复用参考时钟。 时分数据复用系统包括：相位调整单元，用于相互调整具有不同相位的多个数据信号中的每一个的相位，以使数据信号能够在数据的多个值时进行时分复用 信号表示稳定状态; 以及多路复用器根据复用参考时钟对相位调整的数据信号进行时分复用。

公开(公告)号：US07500156B2

公开(公告)日：2009-03-03

申请号：US11417980

申请日：2006-05-04

申请人： Jong Yoon Shin ,  Je Soo Ko

发明人： Jong Yoon Shin ,  Je Soo Ko

IPC分类号： G11B20/20 ,  G11B20/14

CPC分类号： H04L1/242

摘要： A multi-channel data verifying apparatus and method are provided. The apparatus includes a receiver receiving N data channels and a deskew channel generated by sequentially extracting a predetermined data bit from the each of N data channels, and a deskew channel error detector detecting whether the deskew channel received by the receiver corresponds to an expected deskew channel generated and stored based on the test signal or generated based on the previously received deskew channel. Accordingly, data channels, a deskew channel and the entire data capacity can be verified and thus the cause of a problem in the transmission and reception of multi-channel data can be identified in advance.

摘要翻译： 提供了一种多通道数据验证装置和方法。 该装置包括接收N个数据信道的接收机和通过从N个数据信道中的每一个顺序地提取预定的数据位而生成的去歪斜信道，以及歪斜通道误差检测器，检测由接收机接收的歪斜通道是否对应于预期的歪斜通道 基于测试信号生成和存储，或者基于先前接收到的偏移通道生成。 因此，可以验证数据信道，歪斜通道和整个数据容量，因此可以预先识别多信道数据的发送和接收中的问题的原因。