公开(公告)号：US20070098323A1

公开(公告)日：2007-05-03

申请号：US11402150

申请日：2006-04-11

Applicant: Bo Pi ,  Wei-Cheng Lin ,  Zhihao Chen

Inventor： Bo Pi ,  Wei-Cheng Lin ,  Zhihao Chen

IPC: G02B6/26 ,  G02B6/00 ,  G02B6/34 ,  G02B6/42

CPC classification number: G02B6/02057 ,  G01D5/35374 ,  G01K11/3206 ,  G01L9/0076 ,  G01L11/025 ,  G01M3/047 ,  G01N21/774 ,  G01N2021/7736 ,  G01N2021/7773 ,  G02B6/02

Abstract: Fiber sensors formed on side-polished fiber coupling ports based on evanescent coupling are described. Such sensors may be configured to measure various materials and may be used to form multi-phase sensing devices. A Bragg grating may be implemented in such sensors to form reflective fiber sensors.

Abstract translation: 描述了基于ev逝耦合的侧面抛光光纤耦合端口上形成的光纤传感器。 这样的传感器可以被配置为测量各种材料并且可以用于形成多相感测装置。 可以在这样的传感器中实现布拉格光栅以形成反射光纤传感器。

公开(公告)号：US07087887B1

公开(公告)日：2006-08-08

申请号：US10697673

申请日：2003-10-29

Applicant: Bo Pi ,  Shulai Zhao ,  Zhihao Chen

Inventor： Bo Pi ,  Shulai Zhao ,  Zhihao Chen

IPC: G02B6/26

CPC classification number: G02B6/2826

Abstract: Waveguide sensors having a side-polished coupling port at the waveguide cladding to sense a material based on material-specific optical attenuation by evanescent coupling at the coupling port.

Abstract translation: 波导传感器在波导包层处具有侧面抛光的耦合端口，以基于耦合端口处的衰减耦合的材料特定光衰减来感测材料。

公开(公告)号：US07068868B1

公开(公告)日：2006-06-27

申请号：US10714503

申请日：2003-11-12

Applicant: Bo Pi ,  Wei-Cheng Wilson Lin ,  Zhihao Chen ,  Shulai Zhao

Inventor： Bo Pi ,  Wei-Cheng Wilson Lin ,  Zhihao Chen ,  Shulai Zhao

IPC: G02B6/00

CPC classification number: G02B6/2852 ,  G02B6/2826

Abstract: Fiber sensors formed on side-polished fiber coupling ports based on evanescent coupling. Such sensors may be configured to measure various materials and may be used to form multi-phase sensing devices.

Abstract translation: 基于ev逝耦合的在侧面抛光的光纤耦合端口上形成的光纤传感器。 这样的传感器可以被配置为测量各种材料并且可以用于形成多相感测装置。

公开(公告)号：US07060964B1

公开(公告)日：2006-06-13

申请号：US10785718

申请日：2004-02-23

Applicant: Bo Pi ,  Wei-Cheng Wilson Lin ,  Zhihao Chen

Inventor： Bo Pi ,  Wei-Cheng Wilson Lin ,  Zhihao Chen

IPC: G02B6/26

CPC classification number: G02B6/02057 ,  G01D5/35374 ,  G01K11/3206 ,  G01L9/0076 ,  G01L11/025 ,  G01M3/047 ,  G01N21/774 ,  G01N2021/7736 ,  G01N2021/7773 ,  G02B6/02

Abstract: Fiber sensors formed on side-polished fiber coupling ports based on evanescent coupling are described. Such sensors may be configured to measure various materials and may be used to form multi-phase sensing devices. A Bragg grating may be implemented in such sensors to form reflective fiber sensors.

Abstract translation: 描述了基于ev逝耦合的侧面抛光光纤耦合端口上形成的光纤传感器。 这样的传感器可以被配置为测量各种材料并且可以用于形成多相感测装置。 可以在这样的传感器中实现布拉格光栅以形成反射光纤传感器。

公开(公告)号：US06912343B1

公开(公告)日：2005-06-28

申请号：US10268622

申请日：2002-10-09

Applicant: Zhihao Chen ,  Zheng Chen ,  Bo Pi

Inventor： Zhihao Chen ,  Zheng Chen ,  Bo Pi

IPC: G02B6/26 ,  G02B6/30 ,  G02B6/34 ,  G02B6/42

CPC classification number: G02B6/29332 ,  G02B6/266 ,  G02B6/30

Abstract: Adjustable filters formed in fibers or waveguides based on evanescent coupling, where a coupling layer is formed between a waveguide overlay and a side-polished coupling port on the fiber or waveguide. A control mechanism may be provided to adjust a property of at least one of the waveguide overlay and the coupling layer to adjust the output of the filter.

Abstract translation: 基于ev逝耦合的在光纤或波导中形成的可调滤光器，其中耦合层形成在光纤或波导上的波导覆盖层和侧抛光耦合端口之间。 可以提供控制机构来调节波导覆盖层和耦合层中的至少一个的特性以调节滤波器的输出。

公开(公告)号：USD818024S1

公开(公告)日：2018-05-15

申请号：US29569732

申请日：2016-06-30

Applicant: Zhihao Chen

Designer： Zhihao Chen

公开(公告)号：US20120214286A1

公开(公告)日：2012-08-23

申请号：US13171426

申请日：2011-06-28

Applicant: YANGKUI LIN ,  Zhihao Chen

Inventor： YANGKUI LIN ,  Zhihao Chen

IPC: H01L21/336

CPC classification number: H01L21/26506 ,  H01L21/28176 ,  H01L21/324 ,  H01L29/6659 ,  H01L29/7833

Abstract: A method for fabricating an NMOS transistor includes providing a substrate; forming a gate dielectric layer structure on the substrate and forming a gate electrode on the gate dielectric layer structure. The method further includes performing a fluorine ion implantation below the gate dielectric layer and an annealing process in an atmosphere comprising hydrogen or hydrogen plasma. The method also includes forming a source region and a drain region on both sides of the gate electrode before or after the fluorine ion implantation.

Abstract translation: 一种用于制造NMOS晶体管的方法，包括：提供衬底; 在所述衬底上形成栅极电介质层结构，并在所述栅极电介质层结构上形成栅电极。 该方法还包括在栅极电介质层下面进行氟离子注入和在包括氢或氢等离子体的气氛中进行退火处理。 该方法还包括在氟离子注入之前或之后在栅电极的两侧形成源区和漏区。

公开(公告)号：US06524930B1

公开(公告)日：2003-02-25

申请号：US10131958

申请日：2002-04-25

Applicant: Christoph A. Wasshuber ,  Zhihao Chen ,  Freidoon Mehrad

Inventor： Christoph A. Wasshuber ,  Zhihao Chen ,  Freidoon Mehrad

IPC: H01L2176

CPC classification number: H01L21/76235

Abstract: Methods are disclosed for the formation of isolation structures and trenches in semiconductor devices, in which lower corners of an isolation trench are rounded after trench formation using an oxidation process which oxidizes substrate material from the trench sidewalls and bottom faster than from the lower corners of the trench. The oxide formed during the rounding process is then removed prior to performing other etch processes, to expose substrate material having rounded lower corners. Thereafter, a liner is formed and the trench is filled with dielectric material to complete the isolation structure.

Abstract translation: 公开了用于在半导体器件中形成隔离结构和沟槽的方法，其中隔离沟槽的下角在沟槽形成之后被圆化，使用氧化工艺，其从衬底材料从沟槽侧壁氧化衬底，并且底部比从 沟。 然后在进行其它蚀刻工艺之前去除在舍入过程中形成的氧化物，以露出具有圆形下角的衬底材料。 此后，形成衬垫，并且用电介质材料填充沟槽以完成隔离结构。

公开(公告)号：US20050247994A1

公开(公告)日：2005-11-10

申请号：US11178935

申请日：2005-07-11

Applicant: Freidoon Mehrad ,  Zhihao Chen ,  Shashank Ekbote ,  Brian Trentman

Inventor： Freidoon Mehrad ,  Zhihao Chen ,  Shashank Ekbote ,  Brian Trentman

IPC: H01L21/762 ,  H01L29/00

CPC classification number: H01L21/76224

Abstract: Disclosed is a shallow trench isolation (STI) structure and methods of manufacturing the same. The methods eliminate the requirement for design size adjustments (DSA) in manufacturing the STI structure. Further disclosed is an STI trench liner and methods for the formation thereof by growing a thin oxide layer on shallow isolation trench surfaces while preventing oxide formation on adjacent nitride surfaces, followed by the deposition of, and oxide growth upon, a polysilicon layer.

公开(公告)号：US20050062127A1

公开(公告)日：2005-03-24

申请号：US10691843

申请日：2003-10-23

Applicant: Zhihao Chen ,  Freidoon Mehrad ,  Brian Kirkpatrick ,  Jeff White ,  Edmund Russell ,  Jon Holt ,  Jason Mehigan

Inventor： Zhihao Chen ,  Freidoon Mehrad ,  Brian Kirkpatrick ,  Jeff White ,  Edmund Russell ,  Jon Holt ,  Jason Mehigan

IPC: H01L21/316 ,  H01L21/762 ,  H01L29/00

CPC classification number: H01L21/02126 ,  H01L21/02236 ,  H01L21/02238 ,  H01L21/02255 ,  H01L21/31662 ,  H01L21/76235

Abstract: A trench structure in a wafer of semiconductor material and the method of forming the trench structure are described. The trench structure is formed on a semiconductor wafer that has a top surface of slow oxidization rate—slower than that of other major crystallographic planes of the semiconductor material. The trench is etched into the semiconductor wafer. The trench has substantially vertical trench-sidewalls near the top surface, the vertical trench-sidewalls near the top surface containing crystallographic plane that oxidizes at a rate comparable to that of the top surface. An insulating layer is grown on the top surface and on the trench-sidewalls and on corners where sidewall surfaces approach the top surface, the insulating layer at the corners being substantially thicker than at the sidewall adjacent to the corners. The difference in the oxide thickness is due to the faster oxidizing planes exposed at the corners. Finally, the trench is filled with a dielectric material.