摘要:
Device structures and design structures for a static random access memory. The device structure includes a well of a first conductivity type in a semiconductor layer, first and second deep trench isolation regions in the semiconductor layer that laterally bound a device region in the well, and first and second pluralities of doped regions of a second conductivity type in the first device region. A shallow trench isolation region extends laterally across in the device region to connect the first and second deep trench isolation regions, and is disposed in the device region between the first and second pluralities of doped regions. The shallow trench isolation region extends from the top surface into the semiconductor layer to a first depth such that the well is continuous beneath the shallow trench isolation region. A gate stack controls carrier flow between a pair of the first plurality of doped regions.
摘要:
A low power maskless inter-well deep trench isolation structure and methods of manufacture such structure are provided. A method includes depositing a plurality of layers over a substrate, and forming a layer over the plurality of layers. The method also includes forming well structures in the substrate, and forming sidewall spacers at opposing sides of the layer. The method further includes forming a self-aligned deep trench in the substrate to below the well structures, by removing the sidewall spacers and portions of the substrate aligned with an opening formed by the removal of the sidewall spacers. The method also includes forming a shallow trench in alignment with the deep trench. The method further includes forming shallow trench isolation structures and deep trench isolation structures by filling the shallow trench and the deep trench with insulator material.
摘要:
Methods for fabricating dual-depth trench isolation regions for a memory cell. First and second deep trench isolation regions are formed in the semiconductor layer that laterally bound a device region in a well of a first conductivity type in the semiconductor layer. First and second pluralities of doped regions of a second conductivity type are formed in the device region. A shallow trench isolation region is formed that extends laterally across the device region from the first deep trench isolation region to the second deep trench isolation region. The shallow trench isolation region is disposed in the device region between the first and second pluralities of doped regions. The shallow trench isolation region extends into the semiconductor layer to a depth such that the well is continuous beneath the shallow trench isolation region. A gate stack controls carrier flow between a pair of the first plurality of doped regions.
摘要:
A device and method for providing an integrated circuit with a unique identification. The device is usable on an integrated circuit (IC) for generating an identification (ID) identifying the IC and includes a plurality of identification cells each utilizing one of a four wire resistor, thin film resistors, and an inverter pair. A measurement circuit measures a parameter of each cell and is utilized in generating the ID in response thereto.
摘要:
A semiconductor structure fabrication method. The method includes providing a semiconductor structure which includes a first semiconductor layer and a dielectric bottom portion in the first semiconductor layer. A second semiconductor layer on the first semiconductor layer is formed. The first and second semiconductor layers include a semiconductor material. A dielectric top portion and a first STI (Shallow Trench Isolation) region are formed in the second semiconductor layer. The dielectric top portion is in direct physical contact with the dielectric bottom portion.
摘要:
A semiconductor structure fabrication method. The method includes providing a semiconductor structure which includes a first semiconductor layer and a dielectric bottom portion in the first semiconductor layer. A second semiconductor layer on the first semiconductor layer is formed. The first and second semiconductor layers include a semiconductor material. A dielectric top portion and a first STI (Shallow Trench Isolation) region are formed in the second semiconductor layer. The dielectric top portion is in direct physical contact with the dielectric bottom portion.
摘要:
A method of manufacturing and inspecting SOI such that during STI formation, by depositing a light absorbing layer in the STI such as hydrosilicon oxynitride, the silicon inclusions in the buried insulator layer of the SOI are undetectable by an optical inspection. The reduction in background effects allows for improved optical inspection of SOI wafers without having to discriminate against defects created by SOI formation. A method of manufacturing and inspecting semiconductor devices is disclosed wherein deposition of a light absorbing layer, such as hydrosilicon oxynitride, prevents defects occurring prior to deposition from being optically inspectable and those defects created during the most recent processing can be easily distinguished. Also disclosed are an optically inspectable semiconductor device and an optically inspectable semiconductor device having an STI.