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    Method and system for using dynamic random access memory as cache memory
    1.
    发明申请
    Method and system for using dynamic random access memory as cache memory 有权
    使用动态随机存取存储器作为高速缓冲存储器的方法和系统

    公开(公告)号：US20070055818A1

    公开(公告)日：2007-03-08

    申请号：US11595370

    申请日：2006-11-08

    申请人： Brent Keeth ,  Brian Shirley ,  Charles Dennison

    发明人： Brent Keeth ,  Brian Shirley ,  Charles Dennison

    IPC分类号： G06F13/28

    CPC分类号： G06F12/0893 ,  G06F12/0846 ,  G06F12/0897 ,  G11C7/1006 ,  G11C7/1042 ,  G11C11/406 ,  G11C11/409 ,  G11C15/043

    摘要： A cache memory system and method includes a DRAM having a plurality of banks, each of which may be refreshed under control of a refresh controller. In addition to the usual components of a DRAM, the cache memory system also includes 2 SRAMs each having a capacity that is equal to the capacity of each bank of the DRAM. In operation, data read from a bank of the DRAM are stored in one of the SRAMs so that repeated hits to that bank are cached by reading from the SRAM. In the event of a write to a bank that is being refreshed, the write data are stored in one of the SRAMs. After the refresh of the bank has been completed, the data stored in the SRAM are transferred to the DRAM bank. A subsequent read or write to a second DRAM bank undergoing refresh and occurring during the transfer of data from an SRAM to the DRAM is stored in the second bank. If, however, the second bank is being refreshed, the data are stored in the other SRAM. By the time data have been stored in the SRAM, the SRAM previously used to store write data has transferred the data to the first DRAM bank and in thus available to store a subsequent write. Therefore, an SRAM bank is always available to store write data in the event the DRAM bank to which the data are directed is being refreshed.

    摘要翻译： 高速缓冲存储器系统和方法包括具有多个存储体的DRAM，每个存储体可以在刷新控制器的控制下刷新。 除了DRAM的通常部件之外，高速缓冲存储器系统还包括两个SRAM，每个SRAM的容量等于DRAM的每个存储体的容量。 在操作中，从DRAM的存储体读出的数据被存储在一个SRAM中，从而通过从SRAM读取来缓存对该存储体的重复命中。 在写入正在刷新的存储体的情况下，写入数据被存储在一个SRAM中。 在银行刷新完成之后，存储在SRAM中的数据被传送到DRAM存储体。 在从SRAM到DRAM的数据传送期间经历刷新并发生的第二DRAM组的后续读或写存储在第二存储体中。 然而，如果第二个银行被刷新，则数据被存储在另一个SRAM中。 在数据已经存储在SRAM中的时候，先前用于存储写入数据的SRAM已将数据传送到第一DRAM存储体，并因此可用于存储随后的写入。 因此，在刷新数据所指向的DRAM组的情况下，SRAM存储体总是可用于存储写入数据。

    Image viewing device and method of use
    3.
    发明申请
    Image viewing device and method of use 审中-公开
    图像查看装置及使用方法

    公开(公告)号：US20060150460A1

    公开(公告)日：2006-07-13

    申请号：US10850139

    申请日：2004-05-20

    申请人： Roger Lowe ,  Brian Shirley ,  Jason Nokes

    发明人： Roger Lowe ,  Brian Shirley ,  Jason Nokes

    IPC分类号： A47G1/06

    CPC分类号： G09F1/12 ,  G09F19/00 ,  G09F23/00 ,  G09F23/0066

    摘要： An image viewing device that includes a housing, which can be constructed so as to be thematically related to an image to be viewed; a viewing aperture and a light induction aperture located in the housing; a light transmission channel contained within the housing to transmit light from the light induction aperture to the viewing aperture; an image bearing medium; and a media retention device, coupled to the light transmission channel to retain the image bearing medium to allow light to travel from the light induction aperture through the image bearing medium to the viewing aperture. The system may also include a light emission device and/or sound production device, coupled to the housing; a power supply source, coupled to the housing and configured to supply power to the light emission device or the sound production device.

    摘要翻译： 一种图像观看装置，其包括壳体，其可以被构造成与待观看的图像主题相关; 位于壳体中的观察孔和光感应孔; 容纳在所述壳体内以将光从所述光感应孔传送到所述观察孔的光透射通道; 图像承载介质; 以及媒体保持装置，其耦合到所述光传输通道以保持所述图像承载介质，以允许光从所述光感应孔通过所述图像承载介质行进到所述观察孔。 该系统还可以包括耦合到壳体的发光装置和/或声音产生装置; 电源，耦合到壳体并且被配置为向发光装置或声音产生装置供电。

    Method and system for using dynamic random access memory as cache memory
    4.
    发明申请
    Method and system for using dynamic random access memory as cache memory 失效

    公开(公告)号：US20050007848A1

    公开(公告)日：2005-01-13

    申请号：US10912929

    申请日：2004-08-05

    申请人： Brian Shirley

    发明人： Brian Shirley

    IPC分类号： G06F9/00 ,  G06F11/00 ,  G06F12/00 ,  G06F12/08 ,  G11C7/00 ,  G11C11/406

    CPC分类号： G11C11/40603 ,  G06F12/0893 ,  G11C11/406 ,  G11C11/40607

    摘要： A DRAM includes a set of secondary sense amplifiers as well as primary sense amplifiers coupled to respective digit lines of a DRAM array. The secondary sense amplifiers are coupled to the digit lines of an array through isolation transistors so that the secondary sense amplifier can be selectively isolated from the digit lines of an array. The DRAM also includes a refresh controller that periodically refreshes the DRAM on a row-by-row basis, and a command decoder that causes the refresh to be aborted in the even a read or a write command is received by the DRAM during a refresh. The refresh is aborted by saving the data stored in the row being refreshed in the secondary sense amplifiers and then isolating the sense amplifiers from the array. The memory access is then implemented in a normal manner. Since the DRAM can be accessed without waiting for the completion of a refresh in progress, the DRAM can be used as a cache memory in a computer system.

    Dram array with gridded sense amplifier power source for enhanced column repair
    7.
    发明授权
    Dram array with gridded sense amplifier power source for enhanced column repair 有权
    具有网格感知放大器电源的Dram阵列，用于增强色谱柱修复

    公开(公告)号：US06205066B1

    公开(公告)日：2001-03-20

    申请号：US09502822

    申请日：2000-02-11

    申请人： Brian Shirley

    发明人： Brian Shirley

    IPC分类号： G11C700

    CPC分类号： G11C11/4074 ,  G11C7/06 ,  G11C11/4091

    摘要： An apparatus for the supply of power to a gridded array of sense amplifier circuits contained within a memory, e.g., a DRAM, is provided. When the column sensed is operating normally the power source supplies a first voltage to the sense amplifier circuits so that they properly latch the state of an addressed memory cell. When a column has been repaired out the apparatus is capable of driving the sense amplifier circuits with a second voltage so that they are prevented from latching the state of an addressed memory cell, thus avoiding the problems attributable to short circuits between bit and word lines and between the cell plate and bit lines of a memory cell array.

    摘要翻译： 提供了一种用于向包含在存储器（例如DRAM）内的读出放大器电路的网格阵列供电的装置。 当感测到的列正常工作时，电源向读出放大器电路提供第一电压，使得它们适当地锁存寻址的存储器单元的状态。 当列被修复时，装置能够以第二电压驱动读出放大器电路，使得它们被阻止锁定寻址的存储器单元的状态，从而避免了由于位和字线之间的短路引起的问题，以及 在存储单元阵列的单元板和位线之间。

    Method and apparatus for enhancing the performance of semiconductor memory devices
    8.
    发明授权
    Method and apparatus for enhancing the performance of semiconductor memory devices 失效

    公开(公告)号：US6026042A

    公开(公告)日：2000-02-15

    申请号：US58255

    申请日：1998-04-10

    申请人： Brian Shirley ,  Timothy B. Cowles

    发明人： Brian Shirley ,  Timothy B. Cowles

    IPC分类号： G11C7/06 ,  G11C11/4091 ,  G11C7/00

    CPC分类号： G11C7/06 ,  G11C11/4091

    摘要： A method and apparatus for reducing a peak current produced by the simultaneous activation of numerous sense amplifiers associated with an active word line, without reducing the speed of operation of the semiconductor memory device. A memory array includes word lines accessing memory cells and a tracking word line for sequentially activating the sense amplifiers connected to the digit lines by introducing a delay after the activation of each sense amplifier or group of sense amplifiers and before activating the next sense amplifier or group of sense amplifiers, so that the total time for activation of the sense amplifiers for all digit lines associated with an active word line is spread out, but is not longer than the time necessary for activation of an entire word line.