公开(公告)号：US07577212B2

公开(公告)日：2009-08-18

申请号：US10930543

申请日：2004-08-30

申请人： Brent Keeth ,  Joo S. Choi ,  George E. Pax ,  Ronnie M. Harrison ,  David Ovard ,  Dragos Dimitriu ,  Troy A. Manning ,  Roy E. Greeff ,  Greg King ,  Brian Johnson

发明人： Brent Keeth ,  Joo S. Choi ,  George E. Pax ,  Ronnie M. Harrison ,  David Ovard ,  Dragos Dimitriu ,  Troy A. Manning ,  Roy E. Greeff ,  Greg King ,  Brian Johnson

IPC分类号： H03K9/00

CPC分类号： H04L25/062

摘要： A method and system for generating a reference voltage for memory device signal receivers operates in either a calibration mode or a normal operating mode. In the calibration mode, the magnitude of the reference voltage is incrementally varied, and a digital signal pattern is coupled to the receiver at each reference voltage. An output of the receiver is analyzed to determine if the receiver can accurately pass the signal pattern at each reference voltage level. A range of reference voltages that allow the receiver to accurately pass the signal pattern is recorded, and a final reference voltage is calculated at the approximate midpoint of the range. This final reference voltage is applied to the receiver during normal operation.

摘要翻译： 用于产生用于存储器件信号接收器的参考电压的方法和系统以校准模式或正常操作模式工作。 在校准模式下，参考电压的幅度逐渐变化，并且数字信号图案在每个参考电压下耦合到接收器。 分析接收机的输出以确定接收机是否可以在每个参考电压电平下准确地传递信号模式。 记录允许接收器精确地通过信号图案的参考电压范围，并且在该范围的大致中点处计算最终参考电压。 在正常操作期间将该最终参考电压施加到接收器。

公开(公告)号：US07746959B2

公开(公告)日：2010-06-29

申请号：US11433322

申请日：2006-05-11

申请人： Brent Keeth ,  Joo S. Choi ,  George E. Pax ,  Ronnie M. Harrison ,  David Ovard ,  Dragos Dimitriu ,  Troy A. Manning ,  Roy E. Greeff ,  Greg King ,  Brian Johnson

发明人： Brent Keeth ,  Joo S. Choi ,  George E. Pax ,  Ronnie M. Harrison ,  David Ovard ,  Dragos Dimitriu ,  Troy A. Manning ,  Roy E. Greeff ,  Greg King ,  Brian Johnson

IPC分类号： H04L25/06

CPC分类号： H04L25/062

摘要： A method and system for generating a reference voltage for memory device signal receivers operates in either a calibration mode or a normal operating mode. In the calibration mode, the magnitude of the reference voltage is incrementally varied, and a digital signal pattern is coupled to the receiver at each reference voltage. An output of the receiver is analyzed to determine if the receiver can accurately pass the signal pattern at each reference voltage level. A range of reference voltages that allow the receiver to accurately pass the signal pattern is recorded, and a final reference voltage is calculated at the approximate midpoint of the range. This final reference voltage is applied to the receiver during normal operation.

摘要翻译： 用于产生用于存储器件信号接收器的参考电压的方法和系统以校准模式或正常操作模式工作。 在校准模式下，参考电压的幅度逐渐变化，并且数字信号图案在每个参考电压下耦合到接收器。 分析接收机的输出以确定接收机是否可以在每个参考电压电平下准确地传递信号模式。 记录允许接收器精确地通过信号图案的参考电压范围，并且在该范围的大致中点处计算最终参考电压。 在正常操作期间将该最终参考电压施加到接收器。

公开(公告)号：US07549033B2

公开(公告)日：2009-06-16

申请号：US11495418

申请日：2006-07-28

申请人： Joo S. Choi ,  Troy A. Manning ,  Brent Keeth

发明人： Joo S. Choi ,  Troy A. Manning ,  Brent Keeth

IPC分类号： G06F12/00 ,  G06F13/00

CPC分类号： G11C11/4076 ,  G06F12/0207 ,  G06F13/1668 ,  G11C7/1072 ,  G11C7/1078 ,  G11C7/109 ,  G11C11/408 ,  G11C11/409

摘要： A technique to increase transfer rate of command and address signals via a given number of command and address pins in each of one or more integrated circuit memory devices during a clock cycle of a clock signal. In one example embodiment, the command and address signals are sent on both rising and falling edges of a clock cycle of a clock signal to increase the transfer rate and essentially reduce the number of required command and address pins in each integrated circuit memory device.

摘要翻译： 一种在时钟信号的时钟周期期间通过给定数量的一个或多个集成电路存储器件中的每一个中的命令和地址引脚来增加命令和寻址信号的传送速率的技术。 在一个示例实施例中，命令和地址信号在时钟信号的时钟周期的上升沿和下降沿上发送，以增加传输速率，并且基本上减少每个集成电路存储器件中所需的命令和地址引脚的数量。

公开(公告)号：US09324391B2

公开(公告)日：2016-04-26

申请号：US12478270

申请日：2009-06-04

申请人： Joo S. Choi ,  Troy A. Manning ,  Brent Keeth

发明人： Joo S. Choi ,  Troy A. Manning ,  Brent Keeth

IPC分类号： G06F12/02 ,  G11C7/10 ,  G06F13/16

CPC分类号： G11C11/4076 ,  G06F12/0207 ,  G06F13/1668 ,  G11C7/1072 ,  G11C7/1078 ,  G11C7/109 ,  G11C11/408 ,  G11C11/409

摘要： A technique to increase transfer rate of command and address signals via a given number of command and address pins in each of one or more integrated circuit memory devices during a clock cycle of a clock signal. In one example embodiment, the command and address signals are sent on both rising and falling edges of a clock cycle of a clock signal to increase the transfer rate and essentially reduce the number of required command and address pins in each integrated circuit memory device.

摘要翻译： 一种在时钟信号的时钟周期期间通过给定数量的一个或多个集成电路存储器件中的每一个中的命令和地址引脚来增加命令和寻址信号的传送速率的技术。 在一个示例实施例中，命令和地址信号在时钟信号的时钟周期的上升沿和下降沿上发送，以增加传输速率，并且基本上减少每个集成电路存储器件中所需的命令和地址引脚的数量。

公开(公告)号：US20090248970A1

公开(公告)日：2009-10-01

申请号：US12478270

申请日：2009-06-04

申请人： Joo S. Choi ,  Troy A. Manning ,  Brent Keeth

发明人： Joo S. Choi ,  Troy A. Manning ,  Brent Keeth

IPC分类号： G06F12/06 ,  G06F12/04

CPC分类号： G11C11/4076 ,  G06F12/0207 ,  G06F13/1668 ,  G11C7/1072 ,  G11C7/1078 ,  G11C7/109 ,  G11C11/408 ,  G11C11/409

摘要： A technique to increase transfer rate of command and address signals via a given number of command and address pins in each of one or more integrated circuit memory devices during a clock cycle of a clock signal. In one example embodiment, the command and address signals are sent on both rising and falling edges of a clock cycle of a clock signal to increase the transfer rate and essentially reduce the number of required command and address pins in each integrated circuit memory device.

摘要翻译： 一种在时钟信号的时钟周期期间通过给定数量的一个或多个集成电路存储器件中的每一个中的命令和地址引脚来增加命令和寻址信号的传送速率的技术。 在一个示例实施例中，命令和地址信号在时钟信号的时钟周期的上升沿和下降沿上发送，以增加传输速率，并且基本上减少每个集成电路存储器件中所需的命令和地址引脚的数量。

公开(公告)号：US07299329B2

公开(公告)日：2007-11-20

申请号：US10767555

申请日：2004-01-29

申请人： Joo S. Choi ,  Troy A. Manning ,  Brent Keeth

发明人： Joo S. Choi ,  Troy A. Manning ,  Brent Keeth

IPC分类号： G06F12/00

CPC分类号： G11C11/4076 ,  G06F12/0207 ,  G06F13/1668 ,  G11C7/1072 ,  G11C7/1078 ,  G11C7/109 ,  G11C11/408 ,  G11C11/409

摘要： A technique to increase transfer rate of command and address signals via a given number of command and address pins in each of one or more integrated circuit memory devices during a clock cycle of a clock signal. In one example embodiment, the command and address signals are sent on both rising and falling edges of a clock cycle of a clock signal to increase the transfer rate and essentially reduce the number of required command and address pins in each integrated circuit memory device.

摘要翻译： 一种在时钟信号的时钟周期期间通过给定数量的一个或多个集成电路存储器件中的每一个中的命令和地址引脚来增加命令和寻址信号的传送速率的技术。 在一个示例实施例中，命令和地址信号在时钟信号的时钟周期的上升沿和下降沿上发送，以增加传输速率，并且基本上减少每个集成电路存储器件中所需的命令和地址引脚的数量。

公开(公告)号：US06683814B2

公开(公告)日：2004-01-27

申请号：US10278553

申请日：2002-10-22

申请人： Brent Keeth ,  Brian Johnson ,  Troy A. Manning

发明人： Brent Keeth ,  Brian Johnson ,  Troy A. Manning

IPC分类号： G11C700

CPC分类号： G11C7/1072 ,  G11C7/1006 ,  G11C7/1018 ,  G11C7/1027 ,  G11C7/1045 ,  G11C7/1048 ,  G11C7/1051 ,  G11C7/106 ,  G11C7/1066 ,  G11C7/1069 ,  G11C7/1078 ,  G11C11/4093 ,  G11C11/4096 ,  G11C2207/107

摘要： A memory device is operable in either a high mode or a low speed mode. In either mode, 32 bits of data from each of two memory arrays are prefetched into respective sets of 32 flip-flops. In the high-speed mode, the prefetched data bits are transferred in parallel to 4 parallel-to-serial converters, which transform the parallel data bits to a burst of 8 serial data bits and apply the burst to a respective one of 4 data bus terminals. In the low speed mode, two sets of prefetched data bits are transferred in parallel to 8 parallel-to-serial converters, which transform the parallel data bits to a burst of 8 serial data bits and apply the burst to a respective one of 8 data bus terminals.

公开(公告)号：US06882579B2

公开(公告)日：2005-04-19

申请号：US10705388

申请日：2003-11-10

申请人： Brent Keeth ,  Brian Johnson ,  Troy A. Manning

发明人： Brent Keeth ,  Brian Johnson ,  Troy A. Manning

IPC分类号： G11C11/409 ,  G11C7/10 ,  G11C11/407 ,  G11C11/4096 ,  G11C7/00

CPC分类号： G11C7/1072 ,  G11C7/1006 ,  G11C7/1018 ,  G11C7/1027 ,  G11C7/1045 ,  G11C7/1048 ,  G11C7/1051 ,  G11C7/106 ,  G11C7/1066 ,  G11C7/1069 ,  G11C7/1078 ,  G11C11/4093 ,  G11C11/4096 ,  G11C2207/107

摘要： A memory device is operable in either a high mode or a low speed mode. In either mode 32 bits of data from each of two memory arrays are prefetched into respective sets of 32 flip-flops. In the high-speed mode, the prefetched data bits are transferred in parallel to 4 parallel-to-serial converters, which transform the parallel data bits to a burst of 8 serial data bits and apply the burst to a respective one of 4 data bus terminals. In the low speed mode, two sets of prefetched data bits are transferred in parallel to 8 parallel-to-serial converters, which transform the parallel data bits to a burst of 8 serial data bits and apply the burst to a respective one of 8 data bus terminals.

摘要翻译： 存储器件可以在高模式或低速模式下操作。 在任一模式中，来自两个存储器阵列中的每一个的32位数据被预取到相应的32个触发器组中。 在高速模式下，预取数据位并行传输到4个并行到串行转换器，它们将并行数据位转换为8个串行数据位的脉冲串，并将该脉冲串应用于4个数据总线 终端。 在低速模式下，两组预取数据位并行传送到8个并行到串行转换器，它们将并行数据位转换为8个串行数据位的脉冲串，并将该脉冲串应用于8个数据中的相应一个 巴士总站。

公开(公告)号：US06851016B2

公开(公告)日：2005-02-01

申请号：US10720183

申请日：2003-11-25

申请人： Jeffery W. Janzen ,  Brent Keeth ,  Kevin J. Ryan ,  Troy A. Manning ,  Brian Johnson

发明人： Jeffery W. Janzen ,  Brent Keeth ,  Kevin J. Ryan ,  Troy A. Manning ,  Brian Johnson

IPC分类号： G06F12/00 ,  G11C7/10 ,  G11C7/22 ,  G11C11/407

CPC分类号： G11C7/22 ,  G11C7/1072

摘要： In a high speed memory subsystem differences in each memory device's minimum device read latency and differences in signal propagation time between the memory device and the memory controller can result in widely varying system read latencies. The present invention equalizes the system read latencies of every memory device in a high speed memory system by comparing the differences in system read latencies of each device and then operating each memory device with a device system read latency which causes every device to exhibit the same system read latency.

摘要翻译： 在高速存储器子系统中，每个存储器件的最小器件读取延迟和存储器件与存储器控制器之间的信号传播时间差异都会导致系统读取延迟的变化。 本发明通过比较每个设备的系统读取延迟的差异，然后用设备系统读取延迟来操作每个存储器设备来均衡每个存储器设备在高速存储器系统中的系统读取延迟，这使得每个设备呈现相同的系统 读延迟。

公开(公告)号：US06515914B2

公开(公告)日：2003-02-04

申请号：US09814566

申请日：2001-03-21

申请人： Brent Keeth ,  Brian Johnson ,  Troy A. Manning

发明人： Brent Keeth ,  Brian Johnson ,  Troy A. Manning

IPC分类号： G11C700

CPC分类号： G11C7/1072 ,  G11C7/1006 ,  G11C7/1018 ,  G11C7/1027 ,  G11C7/1045 ,  G11C7/1048 ,  G11C7/1051 ,  G11C7/106 ,  G11C7/1066 ,  G11C7/1069 ,  G11C7/1078 ,  G11C11/4093 ,  G11C11/4096 ,  G11C2207/107

摘要： A memory device is operable in either a high mode or a low speed mode. In either mode, 32 bits of data from each of two memory arrays are prefetched into respective sets of 32 flip-flops. In the high-speed mode, the prefetched data bits are transferred in parallel to 4 parallel-to-serial converters, which transform the parallel data bits to a burst of 8 serial data bits and apply the burst to a respective one of 4 data bus terminals. In the low speed mode, two sets of prefetched data bits are transferred in parallel to 8 parallel-to-serial converters, which transform the parallel data bits to a burst of 8 serial data bits and apply the burst to a respective one of 8 data bus terminals.