公开(公告)号：US07577212B2

公开(公告)日：2009-08-18

申请号：US10930543

申请日：2004-08-30

申请人： Brent Keeth ,  Joo S. Choi ,  George E. Pax ,  Ronnie M. Harrison ,  David Ovard ,  Dragos Dimitriu ,  Troy A. Manning ,  Roy E. Greeff ,  Greg King ,  Brian Johnson

发明人： Brent Keeth ,  Joo S. Choi ,  George E. Pax ,  Ronnie M. Harrison ,  David Ovard ,  Dragos Dimitriu ,  Troy A. Manning ,  Roy E. Greeff ,  Greg King ,  Brian Johnson

IPC分类号： H03K9/00

CPC分类号： H04L25/062

摘要： A method and system for generating a reference voltage for memory device signal receivers operates in either a calibration mode or a normal operating mode. In the calibration mode, the magnitude of the reference voltage is incrementally varied, and a digital signal pattern is coupled to the receiver at each reference voltage. An output of the receiver is analyzed to determine if the receiver can accurately pass the signal pattern at each reference voltage level. A range of reference voltages that allow the receiver to accurately pass the signal pattern is recorded, and a final reference voltage is calculated at the approximate midpoint of the range. This final reference voltage is applied to the receiver during normal operation.

摘要翻译： 用于产生用于存储器件信号接收器的参考电压的方法和系统以校准模式或正常操作模式工作。 在校准模式下，参考电压的幅度逐渐变化，并且数字信号图案在每个参考电压下耦合到接收器。 分析接收机的输出以确定接收机是否可以在每个参考电压电平下准确地传递信号模式。 记录允许接收器精确地通过信号图案的参考电压范围，并且在该范围的大致中点处计算最终参考电压。 在正常操作期间将该最终参考电压施加到接收器。

公开(公告)号：US07746959B2

公开(公告)日：2010-06-29

申请号：US11433322

申请日：2006-05-11

申请人： Brent Keeth ,  Joo S. Choi ,  George E. Pax ,  Ronnie M. Harrison ,  David Ovard ,  Dragos Dimitriu ,  Troy A. Manning ,  Roy E. Greeff ,  Greg King ,  Brian Johnson

发明人： Brent Keeth ,  Joo S. Choi ,  George E. Pax ,  Ronnie M. Harrison ,  David Ovard ,  Dragos Dimitriu ,  Troy A. Manning ,  Roy E. Greeff ,  Greg King ,  Brian Johnson

IPC分类号： H04L25/06

CPC分类号： H04L25/062

摘要： A method and system for generating a reference voltage for memory device signal receivers operates in either a calibration mode or a normal operating mode. In the calibration mode, the magnitude of the reference voltage is incrementally varied, and a digital signal pattern is coupled to the receiver at each reference voltage. An output of the receiver is analyzed to determine if the receiver can accurately pass the signal pattern at each reference voltage level. A range of reference voltages that allow the receiver to accurately pass the signal pattern is recorded, and a final reference voltage is calculated at the approximate midpoint of the range. This final reference voltage is applied to the receiver during normal operation.

摘要翻译： 用于产生用于存储器件信号接收器的参考电压的方法和系统以校准模式或正常操作模式工作。 在校准模式下，参考电压的幅度逐渐变化，并且数字信号图案在每个参考电压下耦合到接收器。 分析接收机的输出以确定接收机是否可以在每个参考电压电平下准确地传递信号模式。 记录允许接收器精确地通过信号图案的参考电压范围，并且在该范围的大致中点处计算最终参考电压。 在正常操作期间将该最终参考电压施加到接收器。

公开(公告)号：US20060045206A1

公开(公告)日：2006-03-02

申请号：US10930543

申请日：2004-08-30

申请人： Brent Keeth ,  Joo Choi ,  George Pax ,  Ronnie Harrison ,  David Ovard ,  Dragos Dimitriu ,  Troy Manning ,  Roy Greeff ,  Greg King ,  Brian Johnson

发明人： Brent Keeth ,  Joo Choi ,  George Pax ,  Ronnie Harrison ,  David Ovard ,  Dragos Dimitriu ,  Troy Manning ,  Roy Greeff ,  Greg King ,  Brian Johnson

IPC分类号： H04L27/06

CPC分类号： H04L25/062

摘要： A method and system for generating a reference voltage for memory device signal receivers operates in either a calibration mode or a normal operating mode. In the calibration mode, the magnitude of the reference voltage is incrementally varied, and a digital signal pattern is coupled to the receiver at each reference voltage. An output of the receiver is analyzed to determine if the receiver can accurately pass the signal pattern at each reference voltage level. A range of reference voltages that allow the receiver to accurately pass the signal pattern is recorded, and a final reference voltage is calculated at the approximate midpoint of the range. This final reference voltage is applied to the receiver during normal operation.

公开(公告)号：US20060203938A1

公开(公告)日：2006-09-14

申请号：US11433322

申请日：2006-05-11

申请人： Brent Keeth ,  Joo Choi ,  George Pax ,  Ronnie Harrison ,  David Ovard ,  Dragos Dimitriu ,  Troy Manning ,  Roy Greeff ,  Greg King ,  Brian Johnson

发明人： Brent Keeth ,  Joo Choi ,  George Pax ,  Ronnie Harrison ,  David Ovard ,  Dragos Dimitriu ,  Troy Manning ,  Roy Greeff ,  Greg King ,  Brian Johnson

IPC分类号： H04L25/06

CPC分类号： H04L25/062

摘要： A method and system for generating a reference voltage for memory device signal receivers operates in either a calibration mode or a normal operating mode. In the calibration mode, the magnitude of the reference voltage is incrementally varied, and a digital signal pattern is coupled to the receiver at each reference voltage. An output of the receiver is analyzed to determine if the receiver can accurately pass the signal pattern at each reference voltage level. A range of reference voltages that allow the receiver to accurately pass the signal pattern is recorded, and a final reference voltage is calculated at the approximate midpoint of the range. This final reference voltage is applied to the receiver during normal operation.

公开(公告)号：US06683814B2

公开(公告)日：2004-01-27

申请号：US10278553

申请日：2002-10-22

申请人： Brent Keeth ,  Brian Johnson ,  Troy A. Manning

发明人： Brent Keeth ,  Brian Johnson ,  Troy A. Manning

IPC分类号： G11C700

CPC分类号： G11C7/1072 ,  G11C7/1006 ,  G11C7/1018 ,  G11C7/1027 ,  G11C7/1045 ,  G11C7/1048 ,  G11C7/1051 ,  G11C7/106 ,  G11C7/1066 ,  G11C7/1069 ,  G11C7/1078 ,  G11C11/4093 ,  G11C11/4096 ,  G11C2207/107

摘要： A memory device is operable in either a high mode or a low speed mode. In either mode, 32 bits of data from each of two memory arrays are prefetched into respective sets of 32 flip-flops. In the high-speed mode, the prefetched data bits are transferred in parallel to 4 parallel-to-serial converters, which transform the parallel data bits to a burst of 8 serial data bits and apply the burst to a respective one of 4 data bus terminals. In the low speed mode, two sets of prefetched data bits are transferred in parallel to 8 parallel-to-serial converters, which transform the parallel data bits to a burst of 8 serial data bits and apply the burst to a respective one of 8 data bus terminals.

公开(公告)号：US07310276B2

公开(公告)日：2007-12-18

申请号：US11595515

申请日：2006-11-08

申请人： Brent Keeth ,  Brian Johnson ,  Troy A. Manning

发明人： Brent Keeth ,  Brian Johnson ,  Troy A. Manning

IPC分类号： G11C7/10

CPC分类号： G11C7/1072 ,  G11C7/1006 ,  G11C7/1018 ,  G11C7/1027 ,  G11C7/1045 ,  G11C7/1048 ,  G11C7/1051 ,  G11C7/106 ,  G11C7/1066 ,  G11C7/1069 ,  G11C7/1078 ,  G11C11/4093 ,  G11C11/4096 ,  G11C2207/107

摘要： A memory device is operable in either a high mode or a low speed mode. In either mode 32 bits of data from each of two memory arrays are prefetched into respective sets of 32 flip-flops. In the high-speed mode, the prefetched data bits are transferred in parallel to 4 parallel-to-serial converters, which transform the parallel data bits to a burst of 8 serial data bits and apply the burst to a respective one of 4 data bus terminals. In the low speed mode, two sets of prefetched data bits are transferred in parallel to 8 parallel-to-serial converters, which transform the parallel data bits to a burst of 8 serial data bits and apply the burst to a respective one of 8 data bus terminals.

公开(公告)号：US07160795B2

公开(公告)日：2007-01-09

申请号：US10293789

申请日：2002-11-12

申请人： Shubneesh Batra ,  Michael D. Chaine ,  Brent Keeth ,  Salman Akram ,  Troy A. Manning ,  Brian Johnson ,  Chris G. Martin ,  Todd A. Merritt ,  Eric J. Smith

发明人： Shubneesh Batra ,  Michael D. Chaine ,  Brent Keeth ,  Salman Akram ,  Troy A. Manning ,  Brian Johnson ,  Chris G. Martin ,  Todd A. Merritt ,  Eric J. Smith

IPC分类号： H01L21/44

CPC分类号： H01L24/05 ,  H01L23/5222 ,  H01L24/03 ,  H01L2224/05093 ,  H01L2224/05095 ,  H01L2224/05096 ,  H01L2224/05556 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01007 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01041 ,  H01L2924/01061 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/30105

摘要： A method of reducing parasitic capacitance in an integrated circuit having three or more metal levels is described. The method comprises forming a bond pad at least partially exposed at the top surface of the integrated circuit, forming a metal pad on the metal level below the bond pad and forming an underlying metal pad on each of the one or more lower metal levels. In the illustrated embodiments, the ratio of an area of at least one of the underlying metal pads to the area of the bond pad is less than 30%. Parasitic capacitance is thus greatly reduced and signal propagation speeds improved.

摘要翻译： 描述了一种降低具有三个或更多个金属水平的集成电路中的寄生电容的方法。 该方法包括形成至少部分地暴露在集成电路的顶表面处的接合焊盘，在接合焊盘下方的金属层上形成金属焊盘，并在一个或多个下金属层的每一个上形成下面的金属焊盘。 在所示的实施例中，下面的金属焊盘中的至少一个的面积与焊盘的面积之比小于30％。 寄生电容因此大大降低，信号传播速度提高。

公开(公告)号：US07151707B2

公开(公告)日：2006-12-19

申请号：US11284498

申请日：2005-11-21

申请人： Brent Keeth ,  Brian Johnson ,  Troy A. Manning

发明人： Brent Keeth ,  Brian Johnson ,  Troy A. Manning

IPC分类号： G11C7/00

CPC分类号： G11C7/1072 ,  G11C7/1006 ,  G11C7/1018 ,  G11C7/1027 ,  G11C7/1045 ,  G11C7/1048 ,  G11C7/1051 ,  G11C7/106 ,  G11C7/1066 ,  G11C7/1069 ,  G11C7/1078 ,  G11C11/4093 ,  G11C11/4096 ,  G11C2207/107

摘要： A memory device is operable in either a high mode or a low speed mode. In either mode, 32 bits of data from each of two memory arrays are prefetched into respective sets of 32 flip-flops. In the high-speed mode, the prefetched data bits are transferred in parallel to 4 parallel-to-serial converters, which transform the parallel data bits to a burst of 8 serial data bits and apply the burst to a respective one of 4 data bus terminals. In the low speed mode, two sets of prefetched data bits are transferred in parallel to 8 parallel-to-serial converters, which transform the parallel data bits to a burst of 8 serial data bits and apply the burst to a respective one of 8 data bus terminals.

公开(公告)号：US06842398B2

公开(公告)日：2005-01-11

申请号：US10703275

申请日：2003-11-07

申请人： Brian Johnson ,  Brent Keeth ,  Jeffrey W. Janzen ,  Troy A. Manning ,  Chris G. Martin

发明人： Brian Johnson ,  Brent Keeth ,  Jeffrey W. Janzen ,  Troy A. Manning ,  Chris G. Martin

IPC分类号： G01R31/28 ,  G11C7/10 ,  G11C7/22 ,  G11C11/401 ,  G11C11/407 ,  G11C29/14 ,  G11C8/00

CPC分类号： G11C29/12015 ,  G11C7/1078 ,  G11C7/109 ,  G11C7/22 ,  G11C7/222 ,  G11C29/14

摘要： A synchronous semiconductor memory device is operable in a normal mode and an alternative mode. The semiconductor device has a command bus for receiving a plurality of synchronously captured input signals, and a plurality of asynchronous input terminals for receiving a plurality of asynchronous input signals. The device further has a clock input for receiving an external clock signal thereon, with the device being specified by the manufacturer to be operated in the normal mode using an external clock signal having a frequency no less than a predetermined minimum frequency. An internal delay locked loop (DLL) clocking circuit is coupled to the clock input terminal and is responsive in normal operating mode to be responsive to the external clock signal to generate at least one internal clock signal. control circuitry in the device is responsive to a predetermined sequence of asynchronous signals applied to the device's asynchronous input terminals to place the device in an alternative mode of operation in which the internal clocking circuit is disabled, such that the device may be operated in the alternative mode using an external clock signal having a frequency less than the predetermined minimum frequency. The alternative mode of operation facilitates testing of the device at a speed less than the minimum frequency specified for the normal mode of operation.

公开(公告)号：US06693836B2

公开(公告)日：2004-02-17

申请号：US10278528

申请日：2002-10-22

申请人： Brent Keeth ,  Brian Johnson ,  Troy A. Manning

发明人： Brent Keeth ,  Brian Johnson ,  Troy A. Manning

IPC分类号： G11C700

CPC分类号： G11C7/1072 ,  G11C7/1006 ,  G11C7/1018 ,  G11C7/1027 ,  G11C7/1045 ,  G11C7/1048 ,  G11C7/1051 ,  G11C7/106 ,  G11C7/1066 ,  G11C7/1069 ,  G11C7/1078 ,  G11C11/4093 ,  G11C11/4096 ,  G11C2207/107

摘要： A memory device is operable in either a high mode or a low speed mode. In either mode, 32 bits of data from each of two memory arrays are prefetched into respective sets of 32 flip-flops. In the high-speed mode, the prefetched data bits are transferred in parallel to 4 parallel-to-serial converters, which transform the parallel data bits to a burst of 8 serial data bits and apply the burst to a respective one of 4 data bus terminals. In the low speed mode, two sets of prefetched data bits are transferred in parallel to 8 parallel-to-serial converters, which transform the parallel data bits to a burst of 8 serial data bits and apply the burst to a respective one of 8 data bus terminals.

摘要翻译： 存储器件可以在高模式或低速模式下操作。 在任一模式中，来自两个存储器阵列中的每一个的32位数据被预取到相应的32个触发器组中。 在高速模式下，预取数据位并行传输到4个并行到串行转换器，它们将并行数据位转换为8个串行数据位的脉冲串，并将该脉冲串应用于4个数据总线 终端。 在低速模式下，两组预取数据位并行传送到8个并行到串行转换器，它们将并行数据位转换为8个串行数据位的脉冲串，并将该脉冲串应用于8个数据中的相应一个 巴士总站。