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    Intermediate semiconductor device structure including multiple photoresist layers
    3.
    发明授权
    Intermediate semiconductor device structure including multiple photoresist layers 失效
    包括多个光致抗蚀剂层的中间半导体器件结构

    公开(公告)号：US07078760B2

    公开(公告)日：2006-07-18

    申请号：US10971210

    申请日：2004-10-22

    申请人： Belford T. Coursey ,  Brent D. Gilgen

    发明人： Belford T. Coursey ,  Brent D. Gilgen

    IPC分类号： H01L27/108 ,  H01L29/94

    CPC分类号： G03F7/091 ,  G03F7/0035 ,  G03F7/094 ,  G03F7/11 ,  H01L21/0273

    摘要： The present invention prevents cross-linking between multiple resists that are used in the fabrication of a semiconductor device. In order to prevent resists in close proximity or contact with one another from cross-linking, a non-reactive separation layer is disposed between the resists. The separation layer prevents incompatible components of the resists from reacting with one another. Forming the separation layer between the resists allows a resist located above the separation layer to be polymerized and patterned as desired without patterning another resist located below the separation layer. Methods of patterning multiple resists are also disclosed.

    摘要翻译： 本发明防止在半导体器件的制造中使用的多个抗蚀剂之间的交联。 为了防止彼此紧密接触或彼此接触的抗蚀剂交联，在抗蚀剂之间设置非反应性分离层。 分离层防止抗蚀剂的不相容组分彼此反应。 在抗蚀剂之间形成分离层允许位于分离层上方的抗蚀剂根据需要进行聚合和图案化，而不对位于分离层下方的另一抗蚀剂进行图案化。 还公开了形成多个抗蚀剂的方法。

    Memory circuitry with oxygen diffusion barrier layer received over a well base
    4.
    发明授权
    Memory circuitry with oxygen diffusion barrier layer received over a well base 有权
    具有氧扩散阻挡层的存储电路接收在阱基底上

    公开(公告)号：US07355231B2

    公开(公告)日：2008-04-08

    申请号：US11091260

    申请日：2005-03-28

    申请人： Belford T. Coursey

    发明人： Belford T. Coursey

    IPC分类号： H01L27/108 ,  H01L29/12 ,  H01L31/119 ,  H01L31/00

    CPC分类号： H01L27/10855 ,  H01L27/10894 ,  H01L28/90

    摘要： A method of forming memory circuitry having a memory array having a plurality of memory capacitors and having peripheral memory circuitry operatively configured to write to and read from the memory array, includes forming a dielectric well forming layer over a semiconductor substrate. A portion of the well forming layer is removed effective to form at least one well within the well forming layer. An array of memory cell capacitors is formed within the well. The peripheral memory circuitry is formed laterally outward of the well forming layer memory array well. In one implementation, memory circuitry includes a semiconductor substrate. A plurality of word lines is received over the semiconductor substrate. An insulative layer is received over the word lines and the substrate. The insulative layer has at least one well formed therein. The well has a base received over the word lines. The well peripherally defines an outline of a memory array area. Area peripheral to the well includes memory peripheral circuitry area. A plurality of memory cell storage capacitors is received within the well over the word lines. Peripheral circuitry is received within the peripheral circuitry area and is operatively configured to write to and read from the memory array.

    摘要翻译： 一种形成具有存储器阵列的存储器电路的方法，所述存储器阵列具有多个存储电容器并且具有可操作地配置为写入存储器阵列和从存储器阵列读取的外围存储器电路，包括在半导体衬底上形成电介质阱形成层 去除井形成层的一部分有效地在井形成层内形成至少一个井。 存储单元电容器阵列形成在阱内。 外围存储器电路形成在井形成层存储器阵列的横向外侧。 在一个实现中，存储器电路包括半导体衬底。 多个字线被接收在半导体衬底上。 在字线和衬底上接收绝缘层。 绝缘层在其中形成有至少一个阱。 井底有一个接收字母的基地。 外围界面定义了存储器阵列区域的轮廓。 井的外围区域包括存储器外围电路区域。 多个存储单元存储电容器被接收在该字线内的阱内。 在外围电路区域内接收外围电路，并且可操作地配置为写入存储器阵列并从存储器阵列读取。

    Capacitor for use in an integrated circuit
    5.
    发明授权
    Capacitor for use in an integrated circuit 有权
    用于集成电路的电容器

    公开(公告)号：US07115970B2

    公开(公告)日：2006-10-03

    申请号：US10931718

    申请日：2004-09-01

    申请人： Brent Gilgen ,  Belford T. Coursey

    发明人： Brent Gilgen ,  Belford T. Coursey

    IPC分类号： H01L29/00 ,  H01L21/00

    CPC分类号： H01L28/84 ,  H01L28/91

    摘要： Capacitors for use in an integrated circuit are provided. One aspect of this disclosure relates to a method of making a capacitor. According to various embodiments of the method a bottom electrode adapted to act as an etch stop is formed, a substantially cone-shaped first plate of conductive material is formed having an interior and exterior surface and terminating at the bottom electrode, a layer of dielectric material is formed on at least a portion of the interior and exterior surface of the first plate and substantially conforming to the shape of the first plate, and a second plate of conductive material is formed over the layer of dielectric material. Other aspects and embodiments are provided herein.

    摘要翻译： 提供了用于集成电路的电容器。 本公开的一个方面涉及一种制造电容器的方法。 根据该方法的各种实施例，形成适于用作蚀刻停止件的底部电极，形成具有内部和外部表面并终止于底部电极的大致锥形的第一导电材料板，介电材料层 形成在第一板的内表面和外表面的至少一部分上并且基本上符合第一板的形状，并且在电介质材料层上形成导电材料的第二板。 本文提供了其它方面和实施例。

    Dynamic random access memory circuitry having storage capacitors within a well
    6.
    发明授权
    Dynamic random access memory circuitry having storage capacitors within a well 失效
    在井内具有存储电容器的动态随机存取存储器电路

    公开(公告)号：US07026678B2

    公开(公告)日：2006-04-11

    申请号：US10337817

    申请日：2003-01-06

    申请人： Belford T. Coursey

    发明人： Belford T. Coursey

    IPC分类号： H01L27/108

    CPC分类号： H01L27/10855 ,  H01L27/10894 ,  H01L28/90

    摘要： A method of forming memory circuitry having a memory array having a plurality of memory capacitors and having peripheral memory circuitry operatively configured to write to and read from the memory array, includes forming a dielectric well forming layer over a semiconductor substrate. A portion of the well forming layer is removed effective to form at least one well within the well forming layer. An array of memory cell capacitors is formed within the well. The peripheral memory circuitry is formed laterally outward of the well forming layer memory array well. In one implementation, memory circuitry includes a semiconductor substrate. A plurality of word lines is received over the semiconductor substrate. An insulative layer is received over the word lines and the substrate. The insulative layer has at least one well formed therein. The well has a base received over the word lines. The well peripherally defines an outline of a memory array area. Area peripheral to the well includes memory peripheral circuitry area. A plurality of memory cell storage capacitors is received within the well over the word lines. Peripheral circuitry is received within the peripheral circuitry area and is operatively configured to write to and read from the memory array.

    摘要翻译： 一种形成具有存储器阵列的存储器电路的方法，所述存储器阵列具有多个存储电容器并且具有可操作地配置为写入存储器阵列和从存储器阵列读取的外围存储器电路，包括在半导体衬底上形成电介质阱形成层 去除井形成层的一部分有效地在井形成层内形成至少一个井。 存储单元电容器阵列形成在阱内。 外围存储器电路形成在井形成层存储器阵列的横向外侧。 在一个实现中，存储器电路包括半导体衬底。 多个字线被接收在半导体衬底上。 在字线和衬底上接收绝缘层。 绝缘层在其中形成有至少一个阱。 井底有一个接收字母的基地。 外围界面定义了存储器阵列区域的轮廓。 井的外围区域包括存储器外围电路区域。 多个存储单元存储电容器被接收在该字线内的阱内。 在外围电路区域内接收外围电路，并且可操作地配置为写入存储器阵列并从存储器阵列读取。

    Double-sided capacitor structure for a semiconductor device and a method for forming the structure
    7.
    发明授权
    Double-sided capacitor structure for a semiconductor device and a method for forming the structure 失效
    用于半导体器件的双面电容器结构和用于形成该结构的方法

    公开(公告)号：US06974993B2

    公开(公告)日：2005-12-13

    申请号：US10941735

    申请日：2004-09-13

    申请人： Belford T. Coursey

    发明人： Belford T. Coursey

    IPC分类号： H01L21/02 ,  H01L21/8242 ,  H01L27/108

    CPC分类号： H01L27/10894 ,  H01L27/10814 ,  H01L27/10852 ,  H01L27/10882 ,  H01L28/84 ,  H01L28/91

    摘要： A method used to manufacture a semiconductor device comprises providing a first conductive container capacitor top plate layer and etching the first conductive container capacitor top plate layer to form a plurality of openings therein. Subsequently, a container capacitor bottom plate layer is formed within the plurality of openings in the top plate layer such that the bottom plate layer defines a plurality of openings. A second conductive container capacitor top plate layer is formed within the plurality of openings in the bottom plate layer. The first conductive container capacitor top plate layer is electrically coupled with the second conductive container capacitor top plate layer. The first and second conductive container capacitor top plate layers and the container capacitor bottom plate layer form a plurality of container capacitors. A structure resulting from the method is also disclosed.

    摘要翻译： 用于制造半导体器件的方法包括提供第一导电容器电容器顶板层并蚀刻第一导电容器电容器顶板层以在其中形成多个开口。 随后，在顶板层的多个开口内形成容器电容器底板层，使得底板层限定多个开口。 第二导电容器电容器顶板层形成在底板层中的多个开口内。 第一导电容器电容器顶板层与第二导电容器电容器顶板层电耦合。 第一和第二导电容器电容器顶板层和容器电容器底板层形成多个容器电容器。 还公开了由该方法得到的结构。

    Method of forming memory circuitry
    8.
    发明授权
    Method of forming memory circuitry 有权
    形成存储器电路的方法

    公开(公告)号：US06830972B2

    公开(公告)日：2004-12-14

    申请号：US10241243

    申请日：2002-09-10

    申请人： Belford T. Coursey

    发明人： Belford T. Coursey

    IPC分类号： H01L218242

    CPC分类号： H01L27/10855 ,  H01L27/10894 ,  H01L28/90

    摘要： A method of forming memory circuitry having a memory array having a plurality of memory capacitors and having peripheral memory circuitry operatively configured to write to and read from the memory array, includes forming a dielectric well forming layer over a semiconductor substrate. A portion of the well forming layer is removed effective to form at least one well within the well forming layer. An array of memory cell capacitors is formed within the well. The peripheral memory circuitry is formed laterally outward of the well forming layer memory array well. In one implementation, memory circuitry includes a semiconductor substrate. A plurality of word lines is received over the semiconductor substrate. An insulative layer is received over the word lines and the substrate. The insulative layer has at least one well formed therein. The well has a base received over the word lines. The well peripherally defines an outline of a memory array area. Area peripheral to the well includes memory peripheral circuitry area. A plurality of memory cell storage capacitors is received within the well over the word lines. Peripheral circuitry is received within the peripheral circuitry area and is operatively configured to write to and read from the memory array.

    摘要翻译： 一种形成具有存储器阵列的存储器电路的方法，所述存储器阵列具有多个存储电容器并且具有可操作地配置为写入存储器阵列和从存储器阵列读取的外围存储器电路，包括在半导体衬底上形成电介质阱形成层 去除井形成层的一部分有效地在井形成层内形成至少一个井。 存储单元电容器阵列形成在阱内。 外围存储器电路形成在井形成层存储器阵列的横向外侧。 在一个实现中，存储器电路包括半导体衬底。 多个字线被接收在半导体衬底上。 在字线和衬底上接收绝缘层。 绝缘层在其中形成有至少一个阱。 井底有一个接收字母的基地。 外围界面定义了存储器阵列区域的轮廓。 井的外围区域包括存储器外围电路区域。 多个存储单元存储电容器被接收在该字线内的阱内。 在外围电路区域内接收外围电路，并且可操作地配置为写入存储器阵列并从存储器阵列读取。

    Intermediate semiconductor device structure including multiple photoresist layers
    9.
    发明授权
    Intermediate semiconductor device structure including multiple photoresist layers 失效
    包括多个光致抗蚀剂层的中间半导体器件结构

    公开(公告)号：US07211855B2

    公开(公告)日：2007-05-01

    申请号：US11411575

    申请日：2006-04-25

    申请人： Belford T. Coursey ,  Brent D. Gilgen

    发明人： Belford T. Coursey ,  Brent D. Gilgen

    IPC分类号： H01L21/108 ,  H01L29/94

    CPC分类号： G03F7/091 ,  G03F7/0035 ,  G03F7/094 ,  G03F7/11 ,  H01L21/0273

    摘要： The present invention prevents cross-linking between multiple resists that are used in the fabrication of a semiconductor device. In order to prevent resists in close proximity or contact with one another from cross-linking, a non-reactive separation layer is disposed between the resists. The separation layer prevents incompatible components of the resists from reacting with one another. Forming the separation layer between the resists allows a resist located above the separation layer to be polymerized and patterned as desired without patterning another resist located below the separation layer. Methods of patterning multiple resists are also disclosed.

    摘要翻译： 本发明防止在半导体器件的制造中使用的多个抗蚀剂之间的交联。 为了防止彼此紧密接触或彼此接触的抗蚀剂交联，在抗蚀剂之间设置非反应性分离层。 分离层防止抗蚀剂的不相容组分彼此反应。 在抗蚀剂之间形成分离层允许位于分离层上方的抗蚀剂根据需要进行聚合和图案化，而不对位于分离层下方的另一抗蚀剂进行图案化。 还公开了形成多个抗蚀剂的方法。

    Selective hemispherical silicon grain (HSG) conversion inhibitor for use during the manufacture of a semiconductor device
    10.
    发明授权
    Selective hemispherical silicon grain (HSG) conversion inhibitor for use during the manufacture of a semiconductor device 失效
    在制造半导体器件期间使用的选择性半球形硅晶粒（HSG）转换抑制剂

    公开(公告)号：US06617222B1

    公开(公告)日：2003-09-09

    申请号：US10085689

    申请日：2002-02-27

    申请人： Belford T. Coursey

    发明人： Belford T. Coursey

    IPC分类号： H01L2120

    CPC分类号： H01L28/84 ,  H01L27/10852 ,  H01L28/91

    摘要： A method used to form a semiconductor device comprises forming a layer such as a container capacitor layer having a bottom plate layer. The bottom plate layer is formed to define a receptacle, and a rim which defines an opening to an interior of the receptacle. The bottom plate layer is formed to have a smooth texture. Subsequently, an inhibitor layer is formed on the rim of the bottom plate layer while a majority of the receptacle defined by the bottom plate layer remains free from the inhibitor. With the inhibitor layer on the rim of the bottom plate layer, at least a portion of the receptacle is converted to have a rough texture, such as to hemispherical silicon grain (HSG) polysilicon, while subsequent to the conversion the smooth texture of the rim which defines the opening to the interior of the receptacle remains. A resulting structure is also described.

    摘要翻译： 用于形成半导体器件的方法包括形成诸如具有底板层的容器电容器层的层。 底板层形成为限定一个容器，以及限定到容器内部的开口的边缘。 底板层形成为具有光滑的质地。 随后，在底板层的边缘上形成抑制剂层，而由底板层限定的大部分容器保持不受抑制剂的影响。 通过抑制层在底板层的边缘上，容器的至少一部分被转换为具有粗糙的纹理，例如半球形硅晶粒（HSG）多晶硅，而在转化之后，边缘的平滑纹理 其限定了到容器内部的开口残留。 还描述了所得到的结构。