公开(公告)号：US20070002636A1

公开(公告)日：2007-01-04

申请号：US11173565

申请日：2005-07-01

申请人： Brian Campbell ,  Vincent von Kaenel ,  Daniel Murray ,  Gregory Scott ,  Sribalan Santhanam

发明人： Brian Campbell ,  Vincent von Kaenel ,  Daniel Murray ,  Gregory Scott ,  Sribalan Santhanam

IPC分类号： G11C7/10

CPC分类号： G11C11/419 ,  G11C5/143 ,  G11C7/00 ,  G11C7/12 ,  G11C8/08 ,  G11C11/417 ,  H03K3/35613 ,  H03K19/018528

摘要： In one embodiment, an integrated circuit comprises at least one logic circuit supplied by a first supply voltage and at least one memory circuit coupled to the logic circuit and supplied by a second supply voltage. The memory circuit is configured to be read and written responsive to the logic circuit even if the first supply voltage is less than the second supply voltage during use. In another embodiment, a method comprises a logic circuit reading a memory cell, the logic circuit supplied by a first supply voltage; and the memory cell responding to the read using signals that are referenced to the first supply voltage, wherein the memory cell is supplied with a second supply voltage that is greater than the first supply voltage during use.

摘要翻译： 在一个实施例中，集成电路包括由第一电源电压提供的至少一个逻辑电路和耦合到逻辑电路并由第二电源电压提供的至少一个存储器电路。 即使在使用期间第一电源电压小于第二电源电压，存储器电路被配置为响应于逻辑电路被读取和写入。 在另一个实施例中，一种方法包括读取存储单元的逻辑电路，由第一电源电压提供的逻辑电路; 并且所述存储单元响应于所读取的使用参考于所述第一电源电压的信号，其中所述存储单元被提供在使用期间大于所述第一电源电压的第二电源电压。

公开(公告)号：US07760559B2

公开(公告)日：2010-07-20

申请号：US12325476

申请日：2008-12-01

申请人： Brian J. Campbell ,  Vincent R. von Kaenel ,  Daniel C. Murray ,  Gregory S. Scott ,  Sribalan Santhanam

发明人： Brian J. Campbell ,  Vincent R. von Kaenel ,  Daniel C. Murray ,  Gregory S. Scott ,  Sribalan Santhanam

IPC分类号： G11C7/00

CPC分类号： G11C11/419 ,  G11C5/143 ,  G11C7/00 ,  G11C7/12 ,  G11C8/08 ,  G11C11/417 ,  H03K3/35613 ,  H03K19/018528

摘要： In one embodiment, an integrated circuit comprises at least one logic circuit supplied by a first supply voltage and at least one memory circuit coupled to the logic circuit and supplied by a second supply voltage. The memory circuit is configured to be read and written responsive to the logic circuit even if the first supply voltage is less than the second supply voltage during use. In another embodiment, a method comprises a logic circuit reading a memory cell, the logic circuit supplied by a first supply voltage; and the memory cell responding to the read using signals that are referenced to the first supply voltage, wherein the memory cell is supplied with a second supply voltage that is greater than the first supply voltage during use.

摘要翻译： 在一个实施例中，集成电路包括由第一电源电压提供的至少一个逻辑电路和耦合到逻辑电路并由第二电源电压提供的至少一个存储器电路。 即使在使用期间第一电源电压小于第二电源电压，存储器电路被配置为响应于逻辑电路被读取和写入。 在另一个实施例中，一种方法包括读取存储单元的逻辑电路，由第一电源电压提供的逻辑电路; 并且所述存储单元响应于所读取的使用参考于所述第一电源电压的信号，其中所述存储单元被提供在使用期间大于所述第一电源电压的第二电源电压。

公开(公告)号：US6131107A

公开(公告)日：2000-10-10

申请号：US208169

申请日：1998-12-09

申请人： Gilbert M. Wolrich ,  Sribalan Santhanam ,  Andrew S. Olesin

发明人： Gilbert M. Wolrich ,  Sribalan Santhanam ,  Andrew S. Olesin

IPC分类号： G06F7/52

CPC分类号： G06F7/5312 ,  G06F7/5336 ,  G06F2207/3884 ,  G06F7/483 ,  G06F7/49942 ,  G06F7/49947 ,  G06F7/49994

摘要： A multiplier in a floating point processor includes a circuit to determine for each bit of the multiplier operand a 3 times booth recode and a booth recode multiplier array which implements a 3 times booth recode multiplication. The multiplier includes logic to determine a fast sign extend to replace bit positions shifted in the array as well as a rounding adder to provide a rounded result while determining the final result from the booth recode multiplier. The multiplier also includes a circuit to determine a contribution to the final multiplication result from a lower order product with out forming the entire product.

摘要翻译： 浮点处理器中的乘法器包括一个电路，用于确定乘法器操作数的每一位3次展位重新编码，以及一个实施3次展位重新编码乘法的展位重新编码乘法器阵列。 乘法器包括用于确定快速符号的逻辑，用于替换在阵列中移位的位位置以及舍入加法器，以在确定来自展位重新编码乘数的最终结果的同时提供舍入结果。 乘法器还包括一个电路，用于确定对较低阶乘积的最终相乘结果的贡献，并形成整个乘积。

公开(公告)号：US07990780B2

公开(公告)日：2011-08-02

申请号：US12390247

申请日：2009-02-20

申请人： Honkai Tam ,  Sribalan Santhanam ,  Jung-Cheng Yeh ,  Sanjay P. Zambare

发明人： Honkai Tam ,  Sribalan Santhanam ,  Jung-Cheng Yeh ,  Sanjay P. Zambare

IPC分类号： G11C7/00

CPC分类号： G11C11/419

摘要： A memory circuit may include a pair of cross-coupled inverters configured to store a bit of data and a first transistor coupled to a first node of the pair of cross-coupled inverters. A plurality of transistors that form the pair of inverters have a first nominal threshold voltage. The first transistor is coupled to a first bit line, and has a second nominal threshold voltage that is lower than the first nominal threshold voltage. The first transistor may be a write transistor and another write transistor having the second nominal threshold voltage is coupled to the other node of the pair of cross-coupled inverters. A register file may include a bit storage section that includes at least one pair of the cross-coupled inverters; a write transistor section and a read transistor section having the second nominal threshold voltage.

摘要翻译： 存储器电路可以包括被配置为存储一位数据的一对交叉耦合的反相器，以及耦合到该对交叉耦合的反相器的第一节点的第一晶体管。 形成该对反相器的多个晶体管具有第一标称阈值电压。 第一晶体管耦合到第一位线，并且具有低于第一标称阈值电压的第二标称阈值电压。 第一晶体管可以是写晶体管，并且具有第二标称阈值电压的另一写晶体管耦合到该对交叉耦合反相器对中的另一个节点。 寄存器文件可以包括位存储部分，其包括至少一对交叉耦合的反相器; 写晶体管部分和具有第二标称阈值电压的读晶体管部分。

公开(公告)号：US07355905B2

公开(公告)日：2008-04-08

申请号：US11173565

申请日：2005-07-01

申请人： Brian J. Campbell ,  Vincent R. von Kaenel ,  Daniel C. Murray ,  Gregory S. Scott ,  Sribalan Santhanam

发明人： Brian J. Campbell ,  Vincent R. von Kaenel ,  Daniel C. Murray ,  Gregory S. Scott ,  Sribalan Santhanam

IPC分类号： G11C7/00

CPC分类号： G11C11/419 ,  G11C5/143 ,  G11C7/00 ,  G11C7/12 ,  G11C8/08 ,  G11C11/417 ,  H03K3/35613 ,  H03K19/018528

摘要： In one embodiment, an integrated circuit comprises at least one logic circuit supplied by a first supply voltage and at least one memory circuit coupled to the logic circuit and supplied by a second supply voltage. The memory circuit is configured to be read and written responsive to the logic circuit even if the first supply voltage is less than the second supply voltage during use. In another embodiment, a method comprises a logic circuit reading a memory cell, the logic circuit supplied by a first supply voltage; and the memory cell responding to the read using signals that are referenced to the first supply voltage, wherein the memory cell is supplied with a second supply voltage that is greater than the first supply voltage during use.

摘要翻译： 在一个实施例中，集成电路包括由第一电源电压提供的至少一个逻辑电路和耦合到逻辑电路并由第二电源电压提供的至少一个存储器电路。 即使在使用期间第一电源电压小于第二电源电压，存储器电路被配置为响应于逻辑电路被读取和写入。 在另一个实施例中，一种方法包括读取存储单元的逻辑电路，由第一电源电压提供的逻辑电路; 并且所述存储单元响应于所读取的使用参考于所述第一电源电压的信号，其中所述存储单元被提供有在使用期间大于所述第一电源电压的第二电源电压。

公开(公告)号：US5889692A

公开(公告)日：1999-03-30

申请号：US938951

申请日：1997-09-18

申请人： Gilbert M. Wolrich ,  Sribalan Santhanam ,  Andrew S. Olesin

发明人： Gilbert M. Wolrich ,  Sribalan Santhanam ,  Andrew S. Olesin

IPC分类号： G06F7/52

CPC分类号： G06F7/5312 ,  G06F7/5336 ,  G06F2207/3884 ,  G06F7/483 ,  G06F7/49942 ,  G06F7/49947 ,  G06F7/49994

摘要： A multiplier in a floating point processor includes a circuit to determine for each bit of the multiplier operand a 3 times booth recode and a booth recode multiplier array which implements a 3 times booth recode multiplication. The multiplier includes logic to determine a fast sign extend to replace bit positions shifted in the array as well as a rounding adder to provide a rounded result while determining the final result from the booth recode multiplier. The multiplier also includes a circuit to determine a contribution to the final multiplication result from a lower order product with out forming the entire product.

摘要翻译： 浮点处理器中的乘法器包括一个电路，用于确定乘法器操作数的每一位3次展位重新编码，以及一个实施3次展位重新编码乘法的展位重新编码乘法器阵列。 乘法器包括用于确定快速符号的逻辑，用于替换在阵列中移位的位位置以及舍入加法器，以在确定来自展位重新编码乘数的最终结果的同时提供舍入结果。 乘法器还包括一个电路，用于确定对较低阶乘积的最终相乘结果的贡献，并形成整个乘积。

公开(公告)号：US20100238745A1

公开(公告)日：2010-09-23

申请号：US12791080

申请日：2010-06-01

申请人： Brian J. Campbell ,  Vincent R. von Kaenel ,  Daniel C. Murray ,  Gregory S. Scott ,  Sribalan Santhanam

发明人： Brian J. Campbell ,  Vincent R. von Kaenel ,  Daniel C. Murray ,  Gregory S. Scott ,  Sribalan Santhanam

IPC分类号： G11C7/00

CPC分类号： G11C11/419 ,  G11C5/143 ,  G11C7/00 ,  G11C7/12 ,  G11C8/08 ,  G11C11/417 ,  H03K3/35613 ,  H03K19/018528

摘要： In one embodiment, an integrated circuit comprises at least one logic circuit supplied by a first supply voltage and at least one memory circuit coupled to the logic circuit and supplied by a second supply voltage. The memory circuit is configured to be read and written responsive to the logic circuit even if the first supply voltage is less than the second supply voltage during use. In another embodiment, a method comprises a logic circuit reading a memory cell, the logic circuit supplied by a first supply voltage; and the memory cell responding to the read using signals that are referenced to the first supply voltage, wherein the memory cell is supplied with a second supply voltage that is greater than the first supply voltage during use.

摘要翻译： 在一个实施例中，集成电路包括由第一电源电压提供的至少一个逻辑电路和耦合到逻辑电路并由第二电源电压提供的至少一个存储器电路。 即使在使用期间第一电源电压小于第二电源电压，存储器电路被配置为响应于逻辑电路被读取和写入。 在另一个实施例中，一种方法包括读取存储单元的逻辑电路，由第一电源电压提供的逻辑电路; 并且所述存储单元响应于所读取的使用参考于所述第一电源电压的信号，其中所述存储单元被提供在使用期间大于所述第一电源电压的第二电源电压。

公开(公告)号：US20100214815A1

公开(公告)日：2010-08-26

申请号：US12390247

申请日：2009-02-20

申请人： Honkai Tam ,  Sribalan Santhanam ,  Jung-Cheng Yeh ,  Sanjay P. Zambare

发明人： Honkai Tam ,  Sribalan Santhanam ,  Jung-Cheng Yeh ,  Sanjay P. Zambare

IPC分类号： G11C5/06 ,  G11C11/416

CPC分类号： G11C11/419

摘要： In one embodiment, a memory circuit comprises a pair of cross-coupled inverters configured to store a bit of data and a first transistor coupled to a first node of the pair of cross-coupled inverters. A plurality of transistors that form the pair of inverters have a first nominal threshold voltage. The first transistor is coupled to a first bit line, and has a second nominal threshold voltage that is lower than the first nominal threshold voltage. More specifically, in one embodiment, the first transistor is a write transistor and another write transistor having the second nominal threshold voltage is coupled to the other node of the pair of cross-coupled inverters. In an embodiment, a register file comprises a bit storage section comprising at least one pair of cross-coupled inverters, wherein transistors forming the inverters have a first nominal threshold voltage; a write transistor section comprising a first plurality of transistors; and a read transistor section comprising a second plurality of transistors. The first transistors and the second transistors have a second nominal threshold voltage that is lower than the first nominal threshold voltage. The write transistor section is physically located on a first side of the bit storage section, and the read transistor section is physically located on a second side of the bit storage section opposite the first side.

摘要翻译： 在一个实施例中，存储器电路包括被配置为存储数据位的一对交叉耦合的反相器，以及耦合到所述一对交叉耦合的反相器的第一节点的第一晶体管。 形成该对反相器的多个晶体管具有第一标称阈值电压。 第一晶体管耦合到第一位线，并且具有低于第一标称阈值电压的第二标称阈值电压。 更具体地，在一个实施例中，第一晶体管是写晶体管，并且具有第二标称阈值电压的另一写晶体管耦合到该对交叉耦合反相器对中的另一个节点。 在一个实施例中，寄存器文件包括位存储部分，其包括至少一对交叉耦合的反相器，其中形成反相器的晶体管具有第一标称阈值电压; 写入晶体管部分，包括第一多个晶体管; 以及包括第二多个晶体管的读取晶体管部分。 第一晶体管和第二晶体管具有低于第一标称阈值电压的第二标称阈值电压。 写入晶体管部分物理地位于位存储部分的第一侧，并且读取晶体管部分物理地位于与第一侧相对的位存储部分的第二侧。

公开(公告)号：US20070139098A1

公开(公告)日：2007-06-21

申请号：US11304830

申请日：2005-12-15

申请人： Edgardo Klass ,  Sribalan Santhanam

发明人： Edgardo Klass ,  Sribalan Santhanam

IPC分类号： H03K3/01

CPC分类号： H03K19/0027 ,  H03K19/00384 ,  H03K2217/0018

摘要： In one embodiment, an integrated circuit comprises a first circuit and a control unit coupled to the first circuit. The first circuit comprises at least one transistor and implements one or more operations for which the integrated circuit is designed. The control unit is configured to generate at least one substrate bias voltage for the first circuit.

摘要翻译： 在一个实施例中，集成电路包括耦合到第一电路的第一电路和控制单元。 第一电路包括至少一个晶体管并且实现设计集成电路的一个或多个操作。 控制单元被配置为为第一电路产生至少一个衬底偏置电压。

公开(公告)号：US5729485A

公开(公告)日：1998-03-17

申请号：US526255

申请日：1995-09-11

申请人： Gilbert M. Wolrich ,  Sribalan Santhanam ,  Andrew S. Olesin

发明人： Gilbert M. Wolrich ,  Sribalan Santhanam ,  Andrew S. Olesin

IPC分类号： G06F7/52

CPC分类号： G06F7/5312 ,  G06F7/5336 ,  G06F2207/3884 ,  G06F7/483 ,  G06F7/49942 ,  G06F7/49947 ,  G06F7/49994

摘要： A multiplier in a floating point processor includes a circuit to determine for each bit of the multiplier operand a 3 times booth recode and a booth recode multiplier array which implements a 3 times booth recode multiplication. The multiplier includes logic to determine a fast sign extend to replace bit positions shifted in the array as well as a rounding adder to provide a rounded result while determining the final result from the booth recode multiplier. The multiplier also includes a circuit to determine a contribution to the final multiplication result from a lower order product with out forming the entire product.