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1.发明授权System and method for maintaining cache coherency across a serial interface bus using a snoop request and complete message 有权使用窥探请求和完整消息在串行接口总线上维护高速缓存一致性的系统和方法公开(公告)号：US08782349B2
公开(公告)日：2014-07-15
申请号：US13557980
申请日：2012-07-25
CPC分类号： G06F12/0831
摘要： Techniques are disclosed for maintaining cache coherency across a serial interface bus such as a Peripheral Component Interconnect Express (PCIe) bus. The techniques include generating a snoop request (SNP) to determine whether first data stored in a local memory is coherent relative to second data stored in a data cache, the snoop request including destination information that identifies the data cache on the serial interface bus and causing the snoop request to be transmitted over the serial interface bus to a second processor. The techniques further include extracting a cache line address from the snoop request, determining whether the second data is coherent, generating a complete message (CPL) indicating that the first data is coherent with the second data, and causing the complete message to be transmitted over the bus to the first processor. The snoop request and complete messages may be vendor defined messages.
摘要翻译： 公开了用于通过串行接口总线（例如外围组件互连Express（PCIe）总线）来维持高速缓存一致性的技术。 这些技术包括产生窥探请求（SNP）以确定存储在本地存储器中的第一数据是否相对于存储在数据高速缓存中的第二数据是相干的，该窥探请求包括识别串行接口总线上的数据高速缓存的目的地信息，并导致 通过串行接口总线传送到第二处理器的窥探请求。 所述技术还包括从窥探请求中提取高速缓存线地址，确定第二数据是否相干，生成指示第一数据与第二数据相干的完整消息（CPL），并且使得完整的消息被传送 总线到第一个处理器。 窥探请求和完成消息可以是供应商定义的消息。
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2.发明授权System and method for maintaining cache coherency across a serial interface bus using a snoop request and complete message 有权使用窥探请求和完整消息在串行接口总线上维护高速缓存一致性的系统和方法公开(公告)号：US08234458B2
公开(公告)日：2012-07-31
申请号：US12331302
申请日：2008-12-09
CPC分类号： G06F12/0831
摘要： A method and system for maintaining cache coherency across a serial interface bus such as a Peripheral Component Interconnect Express (PCIe) bus. The method includes generating a snoop request (SNP) to determine whether first data stored in a local memory is coherent relative to second data stored in a data cache, the snoop request including destination information that identifies the data cache on the serial interface bus, and causing the snoop request to be transmitted over the serial interface bus to a second processor. The method further includes extracting a cache line address from the snoop request, determining whether the second data is coherent, generating a complete message (CPL) indicating that the first data is coherent with the second data, and causing the complete message to be transmitted over the bus to the first processor. The snoop request and complete messages may be vendor defined messages.
摘要翻译： 一种用于在串行接口总线（例如外围组件互连Express（PCIe）总线）上维持高速缓存一致性的方法和系统。 该方法包括产生窥探请求（SNP）以确定存储在本地存储器中的第一数据是否相对于存储在数据高速缓冲存储器中的第二数据是相干的，该侦听请求包括识别串行接口总线上的数据高速缓存的目的地信息，以及 导致窥探请求通过串行接口总线传输到第二处理器。 该方法还包括从窥探请求中提取高速缓存线地址，确定第二数据是否相干，生成指示第一数据与第二数据相干的完整消息（CPL），以及使完整消息传输 总线到第一个处理器。 窥探请求和完成消息可以是供应商定义的消息。
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3.发明申请System And Method For Maintaining Cache Coherency Across A Serial Interface Bus 有权通过串行接口总线维护缓存一致性的系统和方法公开(公告)号：US20100146218A1
公开(公告)日：2010-06-10
申请号：US12331302
申请日：2008-12-09
IPC分类号： G06F12/08
CPC分类号： G06F12/0831
摘要： A method for executing processing operations using data stored in a memory. The method includes generating a snoop request configured to determine whether first data stored in a local memory is coherent relative to second data stored in a data cache, the snoop request including destination information that identifies the data cache on a bus, and a cache line address identifying where in the data cache the second data is located. The method further includes causing the snoop request to be transmitted over the bus to the second processor, extracting the cache line address from the snoop request, determining whether the second data is coherent, generating a complete message that includes completion information indicating that the first data is coherent with the second data, and causing the complete message to be transmitted over the bus to the first processor.
摘要翻译： 一种使用存储在存储器中的数据执行处理操作的方法。 该方法包括：生成窥探请求，被配置为确定存储在本地存储器中的第一数据是否相对于存储在数据高速缓存中的第二数据是相干的，该窥探请求包括标识总线上的数据高速缓存的目的地信息和高速缓存行地址 识别第二数据位于数据高速缓存中的位置。 该方法还包括使窥探请求通过总线传送到第二处理器，从窥探请求中提取高速缓存线地址，确定第二数据是否相干，生成完整消息，其中包括指示第一数据的完成信息 与第二数据一致，并且使整个消息通过总线传送到第一处理器。
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公开(公告)号：US07920701B1
公开(公告)日：2011-04-05
申请号：US11304408
申请日：2005-12-14
IPC分类号： H04N7/167
CPC分类号： H04N21/4367 , H04N21/42646 , H04N21/4325 , H04N21/4405 , H04N21/4408
摘要： A digital content system is disclosed. A security engine disposed in a bridge provides cryptographic services. Clear text digital data received from a central processing unit is encrypted and transferred via the bridge over unsecured data paths as cipher text.
摘要翻译： 公开了数字内容系统。 布置在桥中的安全引擎提供加密服务。 从中央处理单元接收到的清除文本数字数据被加密并通过不安全数据路径作为密文通过桥传输。
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公开(公告)号：US08473750B2
公开(公告)日：2013-06-25
申请号：US11304116
申请日：2005-12-14
CPC分类号： H04N21/4367 , G06F21/72 , H04N5/775 , H04N5/85 , H04N5/913 , H04N7/1675 , H04N21/4113 , H04N21/4122 , H04N21/42646 , H04N21/4325 , H04N2005/91364
摘要： A bridge is disclosed having a security engine to protect digital content at insecure interfaces of the bridge. The bridge permits cryptographic services to he offloaded from a central processing unit to the bridge. The bridge receives a clear text input from a central processing unit. The bridge encrypts the clear text input as cipher text for storage in a memory. The bridge provided the cipher text to a graphics processing unit.
摘要翻译： 公开了一种具有安全引擎以在桥的不安全接口处保护数字内容的桥。 该桥允许从中央处理单元卸载到桥上的加密服务。 桥接器从中央处理单元接收明文输入。 桥将加密明文输入作为密文用于存储在内存中。 桥将密文提供给图形处理单元。
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公开(公告)号：US07650645B1
公开(公告)日：2010-01-19
申请号：US11133956
申请日：2005-05-20
CPC分类号： G06F21/606
摘要： Circuits, methods, and apparatus that provide for trusted transactions between a device and system memory. In one exemplary embodiment of the present invention, a host processor asserts and de-asserts trust over a virtual wire. The device accesses certain data if the host processor provides a trusted instruction for it to do so. Once the device attempts to access this certain data, or perform a certain type of data access, a memory controller allows the access on the condition that the host processor previously made the trusted instruction. The device then accepts data if trust is asserted during the data transfer.
摘要翻译： 提供设备和系统存储器之间信任事务的电路，方法和设备。 在本发明的一个示例性实施例中，主机处理器通过虚拟线路断言和取消断言信任。 如果主机处理器为其提供可信指令，则设备访问某些数据。 一旦设备尝试访问该特定数据或执行某种类型的数据访问，存储器控制器允许在主处理器先前做出可信指令的条件下进行访问。 然后，如果在数据传输过程中信任被断言，则设备接受数据。
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公开(公告)号：US07053901B2
公开(公告)日：2006-05-30
申请号：US10732445
申请日：2003-12-11
申请人： Jen-Hsun Huang , Michael Brian Cox , Ziyad S. Hakura , John S. Montrym , Brad W. Simeral , Brian Keith Langendorf , Blanton Scott Kephart , Franck R. Diard
发明人： Jen-Hsun Huang , Michael Brian Cox , Ziyad S. Hakura , John S. Montrym , Brad W. Simeral , Brian Keith Langendorf , Blanton Scott Kephart , Franck R. Diard
IPC分类号： G06T1/00
CPC分类号： G06T1/20 , G06T15/005
摘要： Embodiments of the invention accelerate at least one special purpose processor, such as a GPU, or a driver managing a special purpose processor, by using at least one co-processor. Advantageously, embodiments of the invention are fault-tolerant in that the at least one GPU or other special purpose processor is able to execute all computations, although perhaps at a lower level of performance, if the at least one co-processor is rendered inoperable. The co-processor may also be used selectively, based on performance considerations.
摘要翻译： 本发明的实施例通过使用至少一个协处理器来加速至少一个专用处理器，例如GPU，或者管理专用处理器的驱动器。 有利地，本发明的实施例是容错的，因为如果使至少一个协处理器变得不可操作，则至少一个GPU或其他专用处理器能够执行所有计算，尽管可能处于较低的性能水平。 可以基于性能考虑，有选择地使用协处理器。
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公开(公告)号：US07206902B2
公开(公告)日：2007-04-17
申请号：US10921026
申请日：2004-08-17
申请人： Ziyad S. Hakura , Brian Keith Langendorf , Stefano A. Pescador , Radoslav Danilak , Brad W. Simeral
发明人： Ziyad S. Hakura , Brian Keith Langendorf , Stefano A. Pescador , Radoslav Danilak , Brad W. Simeral
IPC分类号： G06F12/00
CPC分类号： G06F12/0862 , G06F12/0875 , G06F2212/6026
摘要： A system, apparatus, and method are disclosed for predicting accesses to memory. In one embodiment, an exemplary apparatus comprises a processor configured to execute program instructions and process program data, a memory including the program instructions and the program data, and a memory processor. The memory processor can include a speculator configured to receive an address containing the program instructions or the program data. Such a speculator can comprise a sequential predictor for generating a configurable number of sequential addresses. The speculator can also include a nonsequential predictor configured to associate a subset of addresses to the address and to predict a group of addresses based on at least one address of the subset, wherein at least one address of the subset is unpatternable to the address.
摘要翻译： 公开了一种用于预测对存储器的访问的系统，装置和方法。 在一个实施例中，示例性设备包括被配置为执行程序指令和处理程序数据的处理器，包括程序指令和程序数据的存储器以及存储器处理器。 存储器处理器可以包括被配置为接收包含程序指令或程序数据的地址的投机器。 这样的投机者可以包括用于生成可配置数量的顺序地址的顺序预测器。 推测器还可以包括非顺序预测器，其被配置为将地址的子集与地址相关联，并且基于子集的至少一个地址来预测一组地址，其中该子集的至少一个地址对该地址是不可编程的。
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9.发明授权System, apparatus and method for generating nonsequential predictions to access a memory 有权用于生成访问存储器的不相关预测的系统，装置和方法公开(公告)号：US07461211B2
公开(公告)日：2008-12-02
申请号：US10920682
申请日：2004-08-17
申请人： Ziyad S. Hakura , Brian Keith Langendorf , Stefano A. Pescador , Radoslav Danilak , Brad W. Simeral
发明人： Ziyad S. Hakura , Brian Keith Langendorf , Stefano A. Pescador , Radoslav Danilak , Brad W. Simeral
CPC分类号： G06F12/0875 , G06F9/345 , G06F9/383 , G06F9/3832 , G06F12/0862
摘要： A system, apparatus, and method are disclosed for storing and prioritizing predictions to anticipate nonsequential accesses to a memory. In one embodiment, an exemplary apparatus is configured as a prefetcher for predicting accesses to a memory. The prefetcher includes a prediction generator configured to generate a prediction that is unpatternable to an address. Also, the prefetcher also can include a target cache coupled to the prediction generator to maintain the prediction in a manner that determines a priority for the prediction. In another embodiment, the prefetcher can also include a priority adjuster. The priority adjuster sets a priority for a prediction relative to other predictions. In some cases, the placement of the prediction is indicative of the priority relative to priorities for the other predictions. In yet another embodiment, the prediction generator uses the priority to determine that the prediction is to be generated before other predictions.
摘要翻译： 公开了一种系统，装置和方法，用于存储预先确定对存储器的不连续访问的预测的优先级。 在一个实施例中，示例性装置被配置为用于预测对存储器的访问的预取器。 预取器包括被配置为生成对于地址是不可描述的预测的预测生成器。 此外，预取器还可以包括耦合到预测发生器的目标高速缓存以以确定预测的优先级的方式来维持预测。 在另一个实施例中，预取器还可以包括优先级调整器。 优先级调整器设置预测相对于其他预测的优先级。 在某些情况下，预测的放置表示相对于其他预测的优先级的优先级。 在另一个实施例中，预测生成器使用优先级来确定在其它预测之前将产生预测。
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10.发明申请TRAINING, POWER-GATING, AND DYNAMIC FREQUENCY CHANGING OF A MEMORY CONTROLLER 有权记忆控制器的训练，功率增益和动态频率变化公开(公告)号：US20140032947A1
公开(公告)日：2014-01-30
申请号：US13561884
申请日：2012-07-30
申请人： Sagheer Ahmad , Edward L. Riegelsberger , Tony Yuhsiang Cheng , Laurent Rene Moll , Brian Keith Langendorf
发明人： Sagheer Ahmad , Edward L. Riegelsberger , Tony Yuhsiang Cheng , Laurent Rene Moll , Brian Keith Langendorf
IPC分类号： G06F1/00
CPC分类号： G06F1/3275 , G06F9/4418 , Y02D10/14 , Y02D50/20
摘要： A method for managing a memory controller comprising selecting a low-power state from a plurality of low-power states. The method further comprises transitioning to the low-power and entering the low-power state when the transition is complete, provided a wake-event has not been received. An apparatus comprises a controller configured to select a power state for transition, a state-machine configured to execute steps for transitions between power states of a memory controller connected by a bus to a memory, a storage configured to store at least one context, and a context engine configured to stream, at the direction of the state-machine engine, the at least one context to the memory controller. Streaming comprises communicating N portions of context data as a stream to N registers in the memory controller. A context comprises a plurality of calibrations corresponding to a state selected for transition.
摘要翻译： 一种用于管理存储器控制器的方法，包括从多个低功率状态中选择低功率状态。 该方法还包括：当转换完成时，转换到低功率并进入低功率状态，只要没有接收到唤醒事件。 一种装置包括：控制器，被配置为选择用于转换的功率状态;状态机，被配置为执行用于通过总线连接到存储器的存储器控制器的功率状态之间的转换的步骤;被配置为存储至少一个上下文的存储器;以及 上下文引擎，被配置为在所述状态机引擎的方向上将所述至少一个上下文流向所述存储器控制器。 流式传输包括将上下文数据的N个部分作为流传送到存储器控制器中的N个寄存器。 上下文包括对应于选择用于转换的状态的多个校准。
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