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公开(公告)号：US20060294346A1
公开(公告)日：2006-12-28
申请号：US11165268
申请日：2005-06-22
IPC分类号： G06F15/00
CPC分类号： G06F9/3842 , G06F9/30054 , G06F9/3806 , G06F9/3861
摘要： In one or more embodiments, a processor includes a link return stack circuit used for storing branch return addresses, wherein a link return stack controller is configured to determine that one or more entries in the link return stack are invalid as being dependent on a mispredicted branch, and to reset the link return stack to a valid remaining entry, if any. In this manner, branch mispredictions cause dependent entries in the link return stack to be flushed from the link return stack, or otherwise invalidated, while preserving the remaining valid entries, if any, in the link return stack. In at least one embodiment, a branch information queue used for tracking predicted branches is configured to store a marker indicating whether a predicted branch has an associated entry in the link return stack, and it may store an index value identifying the specific, corresponding entry in the link return stack.
摘要翻译： 在一个或多个实施例中，处理器包括用于存储分支返回地址的链路返回堆栈电路，其中，链路返回栈控制器被配置为确定链路返回栈中的一个或多个条目是无效的，这取决于错误预测的分支 ，并将链接返回堆栈重置为有效的剩余条目（如果有）。 以这种方式，分支错误预测会导致链接返回堆栈中的相关条目从链接返回堆栈刷新，否则无效，同时保留链接返回堆栈中的剩余有效条目（如果有的话）。 在至少一个实施例中，用于跟踪预测分支的分支信息队列被配置为存储指示预测分支是否具有链接返回栈中的相关联条目的标记，并且其可以存储标识特定相应条目的索引值 链接返回堆栈。
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公开(公告)号：US20060277397A1
公开(公告)日：2006-12-07
申请号：US11144206
申请日：2005-06-02
IPC分类号： G06F9/44
CPC分类号： G06F9/3844
摘要： A microprocessor includes two branch history tables, and is configured to use a first one of the branch history tables for predicting branch instructions that are hits in a branch target cache, and to use a second one of the branch history tables for predicting branch instructions that are misses in the branch target cache. As such, the first branch history table is configured to have an access speed matched to that of the branch target cache, so that its prediction information is timely available relative to branch target cache hit detection, which may happen early in the microprocessor's instruction pipeline. The second branch history table thus need only be as fast as is required for providing timely prediction information in association with recognizing branch target cache misses as branch instructions, such as at the instruction decode stage(s) of the instruction pipeline.
摘要翻译： 微处理器包括两个分支历史表，并且被配置为使用第一个分支历史表来预测分支目标高速缓存中的命中的分支指令，并且使用第二个分支历史表来预测分支指令， 在分支目标缓存中丢失。 因此，第一分支历史表被配置为具有与分支目标高速缓存的访问速度匹配的访问速度，使得其预测信息相对于可能在微处理器的指令流水线的早期发生的分支目标高速缓存命中检测而及时可用。 因此，第二分支历史表仅需要与将识别分支目标高速缓存未命中作为分支指令（例如在指令流水线的指令解码阶段）相关联地提供及时的预测信息所需的速度。
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3.发明申请Power saving methods and apparatus to selectively enable cache bits based on known processor state 有权省电方法和装置，用于基于已知的处理器状态选择性地启用高速缓存位公开(公告)号：US20060200686A1
公开(公告)日：2006-09-07
申请号：US11073284
申请日：2005-03-04
IPC分类号： G06F1/26
CPC分类号： G06F9/382 , G06F9/30152 , G06F9/3816 , G06F12/0875 , Y02D10/13
摘要： A processor capable of fetching and executing variable length instructions is described having instructions of at least two lengths. The processor operates in multiple modes. One of the modes restricts instructions that can be fetched and executed to the longer length instructions. An instruction cache is used for storing variable length instructions and their associated predecode bit fields in an instruction cache line and storing the instruction address and processor operating mode state information at the time of the fetch in a tag line. The processor operating mode state information indicates the program specified mode of operation of the processor. The processor fetches instructions from the instruction cache for execution. As a result of an instruction fetch operation, the instruction cache may selectively enable the writing of predecode bit fields in the instruction cache and may selectively enable the reading of predecode bit fields stored in the instruction cache based on the processor state at the time of the fetch.
摘要翻译： 描述具有至少两个长度的指令的能够获取和执行可变长度指令的处理器。 处理器以多种模式运行。 其中一种模式限制了可以获取并执行到较长长度指令的指令。 指令高速缓存用于在指令高速缓存行中存储可变长度指令及其相关联的预解码位字段，并且在获取标签行时存储指令地址和处理器操作模式状态信息。 处理器操作模式状态信息指示处理器的程序指定的操作模式。 处理器从指令缓存器中获取指令以执行。 作为指令提取操作的结果，指令高速缓存可以选择性地启用指令高速缓存中的预解码位字段的写入，并且可以基于处理器状态来选择性地启用存储在指令高速缓存中的预解码位字段的读取 取。
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公开(公告)号：US20070067574A1
公开(公告)日：2007-03-22
申请号：US11233575
申请日：2005-09-21
申请人： Brian Stempel , James Dieffenderfer , Jeffrey Bridges , Thomas Sartorius , Rodney Smith , Robert Clancy , Victor Augsburg
发明人： Brian Stempel , James Dieffenderfer , Jeffrey Bridges , Thomas Sartorius , Rodney Smith , Robert Clancy , Victor Augsburg
IPC分类号： G06F12/00
CPC分类号： G06F12/126
摘要： A method of managing cache partitions provides a first pointer for higher priority writes and a second pointer for lower priority writes, and uses the first pointer to delimit the lower priority writes. For example, locked writes have greater priority than unlocked writes, and a first pointer may be used for locked writes, and a second pointer may be used for unlocked writes. The first pointer is advanced responsive to making locked writes, and its advancement thus defines a locked region and an unlocked region. The second pointer is advanced responsive to making unlocked writes. The second pointer also is advanced (or retreated) as needed to prevent it from pointing to locations already traversed by the first pointer. Thus, the pointer delimits the unlocked region and allows the locked region to grow at the expense of the unlocked region.
摘要翻译： 管理高速缓存分区的方法提供用于较高优先级写入的第一指针和用于较低优先级写入的第二指针，并且使用第一指针来划分较低优先级的写入。 例如，锁定的写入具有比解锁的写入更高的优先级，并且第一指针可以用于锁定的写入，并且第二指针可以用于解锁的写入。 响应于锁定写入，第一指针是高级的，并且其进步因此定义了锁定区域和解锁区域。 响应于解锁写入，第二个指针是高级的。 第二个指针也根据需要进行高级（或撤销），以防止它指向已经被第一个指针所遍历的位置。 因此，指针限定未锁定区域，并允许锁定区域以解锁区域为代价而增长。
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公开(公告)号：US20060200655A1
公开(公告)日：2006-09-07
申请号：US11073283
申请日：2005-03-04
IPC分类号： G06F9/00
CPC分类号： G06F12/1063 , G06F9/321 , G06F9/3806 , G06F9/3844 , G06F12/0862 , G06F12/0875 , G06F2212/6028
摘要： A pipelined processor comprises an instruction cache (iCache), a branch target address cache (BTAC), and processing stages, including a stage to fetch from the iCache and the BTAC. To compensate for the number of cycles needed to fetch a branch target address from the BTAC, the fetch from the BTAC leads the fetch of a branch instruction from the iCache by an amount related to the cycles needed to fetch from the BTAC. Disclosed examples either decrement a write address of the BTAC or increment a fetch address of the BTAC, by an amount essentially corresponding to one less than the cycles needed for a BTAC fetch.
摘要翻译： 流水线处理器包括指令高速缓存（iCache），分支目标地址缓存（BTAC）和处理阶段，包括从iCache和BTAC获取的阶段。 为了补偿从BTAC获取分支目标地址所需的周期数，从BTAC的提取导致从iCache获取分支指令与从BTAC获取所需的周期相关的量。 所公开的示例可以减少BTAC的写入地址或增加BTAC的获取地址，其量基本上对应于比BTAC提取所需的周期少一个量。
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公开(公告)号：US20070094475A1
公开(公告)日：2007-04-26
申请号：US11254873
申请日：2005-10-20
IPC分类号： G06F12/00
CPC分类号： G06F12/1063 , G06F12/1054 , G06F12/145 , Y02D10/13
摘要： A processing system may include a memory configured to store data in a plurality of pages, a TLB, and a memory cache including a plurality of cache lines. Each page in the memory may include a plurality of lines of memory. The memory cache may permit, when a virtual address is presented to the cache, a matching cache line to be identified from the plurality of cache lines, the matching cache line having a matching address that matches the virtual address. The memory cache may be configured to permit one or more page attributes of a page located at the matching address to be retrieved from the memory cache and not from the TLB, by further storing in each one of the cache lines a page attribute of the line of data stored in the cache line.
摘要翻译： 处理系统可以包括被配置为在多个页面中存储数据的存储器，TLB和包括多个高速缓存行的存储器高速缓存。 存储器中的每个页面可以包括多行存储器。 当虚拟地址被呈现给高速缓存时，存储器高速缓存可以允许要从多条高速缓存行识别的匹配高速缓存行，匹配高速缓存行具有与虚拟地址匹配的匹配地址。 存储器高速缓存可以被配置为允许通过在高速缓存行的每一个中存储行的页面属性来允许位于匹配地址的页面的一个或多个页面属性从存储器高速缓存而不是从TLB检索， 的数据存储在缓存行中。
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公开(公告)号：US20060123326A1
公开(公告)日：2006-06-08
申请号：US10995858
申请日：2004-11-22
IPC分类号： H03M13/03
CPC分类号： G06F9/3861 , G06F9/30152 , G06F9/3017 , G06F9/382
摘要： In a pipelined processor where instructions are pre-decoded prior to being stored in a cache, an incorrectly pre-decoded instruction is detected during execution in the pipeline. The corresponding instruction is invalidated in the cache, and the instruction is forced to evaluate as a branch instruction. In particular, the branch instruction is evaluated as “mispredicted not taken” with a branch target address of the incorrectly pre-decoded instruction's address. This, with the invalidated cache line, causes the incorrectly pre-decoded instruction to be re-fetched from memory with a precise address. The re-fetched instruction is then correctly pre-decoded, written to the cache, and executed.
摘要翻译： 在流水线处理器中，在将存储在高速缓存中的指令进行预解码之前，在流水线执行期间检测到未正确预解码的指令。 相应的指令在缓存中无效，并且强制将该指令作为分支指令进行求值。 特别地，分支指令被评估为未被错误地预解码的指令的地址的分支目标地址“未被采用”。 这使得无效的高速缓存行导致错误地预解码的指令从具有精确地址的存储器重新获取。 然后重新获取的指令被正确预解码，写入高速缓存并执行。
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8.发明申请Translation lookaside buffer (TLB) suppression for intra-page program counter relative or absolute address branch instructions 有权翻译后备缓冲器（TLB）抑制用于页内程序计数器相对或绝对地址分支指令公开(公告)号：US20060149981A1
公开(公告)日：2006-07-06
申请号：US11003772
申请日：2004-12-02
IPC分类号： G06F1/32
CPC分类号： G06F12/1027 , G06F9/30054 , G06F9/32 , G06F9/3804 , G06F9/382 , G06F2212/1028 , G06F2212/655 , Y02D10/13
摘要： In a pipelined processor, a pre-decoder in advance of an instruction cache calculates the branch target address (BTA) of PC-relative and absolute address branch instructions. The pre-decoder compares the BTA with the branch instruction address (BIA) to determine whether the target and instruction are in the same memory page. A branch target same page (BTSP) bit indicating this is written to the cache and associated with the instruction. When the branch is executed and evaluated as taken, a TLB access to check permission attributes for the BTA is suppressed if the BTA is in the same page as the BIA, as indicated by the BTSP bit. This reduces power consumption as the TLB access is suppressed and the BTA/BIA comparison is only performed once, when the branch instruction is first fetched. Additionally, the pre-decoder removes the BTA/BIA comparison from the BTA generation and selection critical path.
摘要翻译： 在流水线处理器中，在指令高速缓存之前的预解码器计算PC相对的分支目标地址（BTA）和绝对地址分支指令。 预解码器将BTA与分支指令地址（BIA）进行比较，以确定目标和指令是否在相同的存储器页面中。 指示这一点的分支目标相同页（BTSP）位被写入高速缓存并与指令相关联。 当分支被执行并被评估时，如果BTA与BIA位于同一页面中，则由B BTS指示的TLB访问来检查BTA的许可属性被抑制。 当首先取出分支指令时，这样可以降低TLB访问的功耗，并且仅执行一次BTA / BIA比较。 另外，预解码器从BTA生成和选择关键路径去除BTA / BIA比较。
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公开(公告)号：US20070204142A1
公开(公告)日：2007-08-30
申请号：US11363072
申请日：2006-02-27
IPC分类号： G06F15/00
CPC分类号： G06F9/3844 , G06F9/30054 , G06F9/3806 , G06F9/3842 , G06F9/3861
摘要： A link stack in a processor is repaired in response to a procedure return address misprediction error. In one example, a link stack for use in a processor is repaired by detecting an error in a procedure return address value retrieved from the link stack and skipping a procedure return address value currently queued for retrieval from the link stack responsive to detecting the error. In one or more embodiments, a link stack circuit comprises a link stack and a link stack pointer. The link stack is configured to store a plurality of procedure return address values. The link stack pointer is configured to skip a procedure return address value currently queued for retrieval from the link stack responsive to an error detected in a procedure return address value previously retrieved from the link stack.
摘要翻译： 响应于过程返回地址错误预测错误，处理器中的链路堆栈被修复。 在一个示例中，通过检测从链接堆栈检索到的过程返回地址值中的错误来修复处理器中使用的链接栈，并且响应于检测到错误，跳过当前排队等待从链接堆栈检索的过程返回地址值。 在一个或多个实施例中，链路栈电路包括链路栈和链路栈指针。 链路栈被配置为存储多个过程返回地址值。 链路堆栈指针被配置为响应于先前从链路栈检索的过程返回地址值中检测到的错误，跳过当前排队等待从链路栈检索的过程返回地址值。
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10.发明申请公开(公告)号：US20060265572A1
公开(公告)日：2006-11-23
申请号：US11132749
申请日：2005-05-18
申请人： Brian Stempel , Jeffrey Bridges , Rodney Smith , Thomas Sartorius
发明人： Brian Stempel , Jeffrey Bridges , Rodney Smith , Thomas Sartorius
IPC分类号： G06F9/30
CPC分类号： G06F9/30149 , G06F9/30047 , G06F9/30181 , G06F9/3802 , G06F9/3814 , G06F9/3816 , G06F9/3875 , G06F12/0875 , G06F12/0886 , G06F2212/655
摘要： A fetch section of a processor comprises an instruction cache and a pipeline of several stages for obtaining instructions. Instructions may cross cache line boundaries. The pipeline stages process two addresses to recover a complete boundary crossing instruction. During such processing, if the second piece of the instruction is not in the cache, the fetch with regard to the first line is invalidated and recycled. On this first pass, processing of the address for the second part of the instruction is treated as a pre-fetch request to load instruction data to the cache from higher level memory, without passing any of that data to the later stages of the processor. When the first line address passes through the fetch stages again, the second line address follows in the normal order, and both pieces of the instruction are can be fetched from the cache and combined in the normal manner.
摘要翻译： 处理器的获取部分包括指令高速缓存和用于获取指令的若干级的流水线。 指令可能会跨越缓存行边界。 流水线处理两个地址以恢复完整的边界交叉指令。 在这种处理过程中，如果第二条指令不在高速缓存中，则关于第一行的提取将被无效再循环。 在该第一遍中，对于指令的第二部分的地址的处理被视为从高级存储器将指令数据加载到高速缓存的预取请求，而不将该数据传递到处理器的后期。 当第一行地址再次通过读取级时，第二行地址以正常顺序跟随，并且可以从高速缓存中取出两条指令并以正常方式进行组合。
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