公开(公告)号：US20140299964A1

公开(公告)日：2014-10-09

申请号：US14246579

申请日：2014-04-07

Applicant: Broadcom Corporation

Inventor： Henry Kuo-Shun CHEN ,  Guang-Jye Shiau ,  Akira Ito

IPC: H01L49/02

CPC classification number: H01L28/10 ,  H01F5/00 ,  H01F17/0013 ,  H01F41/041 ,  H01L23/5227 ,  H01L23/525 ,  H01L24/10 ,  H01L24/13 ,  H01L27/08 ,  H01L2224/05022 ,  H01L2224/05027 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05572 ,  H01L2224/056 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2224/16 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/19042 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/00 ,  H01L2924/00014

Abstract: A system and method utilize a redistribution layer in a flip-chip or wirebond package, which is also used to route signals to bumps, as a layer for the construction of an on-chip inductor or a layer of a multiple-layer on-chip inductor. In one example, the redistribution layer is surrounded by dual-layer passivation to protect it, and the inductor formed thereby, from the environment and isolate it, and the inductor formed thereby, from the metal layer beneath it.

Abstract translation: 一种系统和方法利用倒装芯片或引线键合封装中的再分布层，其也用于将信号路由到凸点，作为用于构建片上电感器的层或多层片上层 电感。 在一个示例中，再分布层被双层钝化包围，以保护它，并且从环境形成的电感器从其环境中分离出来并将其与其形成的电感器从其下方的金属层隔离开来。

公开(公告)号：US20140084368A1

公开(公告)日：2014-03-27

申请号：US14093695

申请日：2013-12-02

Applicant: Broadcom Corporation

Inventor： Akira ITO ,  Henry Kuo-Shun CHEN

IPC: H01L29/78 ,  H01L29/10

CPC classification number: H01L29/7816 ,  H01L29/0653 ,  H01L29/086 ,  H01L29/0865 ,  H01L29/1045 ,  H01L29/1083 ,  H01L29/456 ,  H01L29/66659 ,  H01L29/7835

Abstract: Optimization of the implantation structure of a metal oxide silicon field effect transistor (MOSFET) device fabricated using conventional complementary metal oxide silicon (CMOS) logic foundry technology to increase the breakdown voltage. The techniques used to optimize the implantation structure involve lightly implanting the gate region, displacing the drain region from the gate region, and implanting P-well and N-well regions adjacent to one another without an isolation region in between.

Abstract translation: 优化使用常规互补金属氧化物硅（CMOS）逻辑铸造技术制造的金属氧化物硅场效应晶体管（MOSFET）器件的注入结构，以增加击穿电压。 用于优化注入结构的技术包括轻微地注入栅极区域，使漏极区域从栅极区域移位，以及将P阱和N阱区域彼此相邻地注入，而不会在其间形成隔离区域。