公开(公告)号：US09337188B2

公开(公告)日：2016-05-10

申请号：US14072723

申请日：2013-11-05

Applicant: Broadcom Corporation

Inventor： Shom Surendran Ponoth ,  Changyok Park ,  Guang-Jye Shiau ,  Akira Ito

IPC: H01L49/02 ,  H01L27/08 ,  H01L27/108 ,  H01L23/522 ,  H01L27/06

CPC classification number: H01L27/0629 ,  H01L23/5223 ,  H01L27/0805 ,  H01L27/10855 ,  H01L28/40 ,  H01L28/60 ,  H01L28/90 ,  H01L29/0649 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A capacitor structure in a semiconductor device includes a semiconductor substrate having a top surface and a bottom surface opposite the top surface, an isolation region having a top surface and a bottom surface, opposite the top surface, the bottom surface of the isolation region being disposed on the top surface of the semiconductor substrate. The capacitor structure also includes a gate terminal structure disposed on the top surface of the isolation region and a diffusion contact structure disposed on the top surface of the isolation region and arranged parallel to the gate terminal structure. In some aspects, the gate terminal structure is connected to a first contact node and the diffusion contact structure is connected to a second contact node, in which the first and second contact nodes form opposing nodes of the capacitor structure.

Abstract translation: 半导体器件中的电容器结构包括具有顶表面和与顶表面相对的底表面的半导体衬底，隔离区域具有与顶表面相对的顶表面和底表面，隔离区域的底表面设置 在半导体衬底的顶表面上。 电容器结构还包括设置在隔离区域的顶表面上的栅极端子结构和设置在隔离区域的顶表面上且平行于栅极端子结构设置的扩散接触结构。 在一些方面，栅极端子结构连接到第一接触节点，并且扩散接触结构连接到第二接触节点，其中第一和第二接触节点形成电容器结构的相对节点。

公开(公告)号：US20140299964A1

公开(公告)日：2014-10-09

申请号：US14246579

申请日：2014-04-07

Applicant: Broadcom Corporation

Inventor： Henry Kuo-Shun CHEN ,  Guang-Jye Shiau ,  Akira Ito

IPC: H01L49/02

CPC classification number: H01L28/10 ,  H01F5/00 ,  H01F17/0013 ,  H01F41/041 ,  H01L23/5227 ,  H01L23/525 ,  H01L24/10 ,  H01L24/13 ,  H01L27/08 ,  H01L2224/05022 ,  H01L2224/05027 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05572 ,  H01L2224/056 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2224/16 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/19042 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/00 ,  H01L2924/00014

Abstract: A system and method utilize a redistribution layer in a flip-chip or wirebond package, which is also used to route signals to bumps, as a layer for the construction of an on-chip inductor or a layer of a multiple-layer on-chip inductor. In one example, the redistribution layer is surrounded by dual-layer passivation to protect it, and the inductor formed thereby, from the environment and isolate it, and the inductor formed thereby, from the metal layer beneath it.

Abstract translation: 一种系统和方法利用倒装芯片或引线键合封装中的再分布层，其也用于将信号路由到凸点，作为用于构建片上电感器的层或多层片上层 电感。 在一个示例中，再分布层被双层钝化包围，以保护它，并且从环境形成的电感器从其环境中分离出来并将其与其形成的电感器从其下方的金属层隔离开来。