公开(公告)号：US06453376B1

公开(公告)日：2002-09-17

申请号：US09521334

申请日：2000-03-09

申请人： Bruce A. Fairman ,  Scott D. Smyers ,  Harold A. Ludtke ,  Glen D. Stone

发明人： Bruce A. Fairman ,  Scott D. Smyers ,  Harold A. Ludtke ,  Glen D. Stone

IPC分类号： G06F1200

CPC分类号： G06F9/485 ,  G06F9/4881 ,  G06F2209/485

摘要： A method for implementing scheduling mechanisms with selectable resource modes comprises at least one resource characterization set that includes a plurality of resource characterizations that each have resource requirements for executing a requested process. The plurality of resource characterizations may include a most mode, a best mode, and a worst mode. An allocation manager may then select a resource mode, and compare the corresponding resource requirements for the requested process to the currently-available device resources. The allocation manager may then authorize or deny the requested process depending upon whether the currently-available resources are sufficient to adequately service the resource requirements of the requested process.

摘要翻译： 用于用可选资源模式实现调度机制的方法包括至少一个资源表征集合，其包括多个资源表征，每个资源表征都具有用于执行所请求的进程的资源需求。 多个资源表征可以包括大多数模式，最佳模式和最差模式。 然后，分配管理器可以选择资源模式，并将所请求进程的相应资源需求与当前可用的设备资源进行比较。 然后，分配管理器可以根据当前可用的资源是否足以充分地满足所请求进程的资源需求来授权或拒绝所请求的进程。

公开(公告)号：US06973653B1

公开(公告)日：2005-12-06

申请号：US09521308

申请日：2000-03-09

申请人： Bruce A. Fairman ,  Scott D. Smyers ,  Harold A. Ludtke ,  Glen D. Stone

发明人： Bruce A. Fairman ,  Scott D. Smyers ,  Harold A. Ludtke ,  Glen D. Stone

IPC分类号： H04J3/24 ,  G06F7/00 ,  G06F9/46 ,  G06F9/50 ,  H01L20060101 ,  H04Q11/00

CPC分类号： G06F9/485 ,  G06F9/4881 ,  G06F2209/485

摘要： A method for providing optimal performance in an electronic device comprises at least one resource characterization that includes resource requirements for executing a requested process. An allocation manager may then compare the resource requirements for the requested process to the currently-available device resources. The allocation manager may then authorize or deny the requested process depending upon whether the currently-available resources are sufficient to adequately service the resource requirements of the requested process.

摘要翻译： 用于在电子设备中提供最佳性能的方法包括至少一种资源表征，其包括用于执行所请求的过程的资源需求。 然后，分配管理器可以将所请求进程的资源需求与当前可用的设备资源进行比较。 然后，分配管理器可以根据当前可用的资源是否足以充分地满足所请求进程的资源需求来授权或拒绝所请求的进程。

公开(公告)号：US06952826B1

公开(公告)日：2005-10-04

申请号：US09691879

申请日：2000-10-18

申请人： Scott D. Smyers ,  Bruce A. Fairman ,  Glen D. Stone ,  Harold A. Ludtke

发明人： Scott D. Smyers ,  Bruce A. Fairman ,  Glen D. Stone ,  Harold A. Ludtke

IPC分类号： G06F9/46 ,  G06F9/48

CPC分类号： G06F9/4881

摘要： A method for implementing a multi-level system model for deterministically handling selected data comprises a picokernel module that invokes an isochronous scheduler to select, schedule, and execute active isochronous processes on an electronic device in response to a cycle start signal from an isochronous clock. The active isochronous processes may selectively set plesiochronous flags to thereby designate corresponding plesiochronous processes as active plesiochronous processes. Once all active isochronous processes have been executed in a given isochronous cycle, then the picokernel may invoke a plesiochronous scheduler to select, schedule, and execute any active plesiochronous processes on the electronic device.

摘要翻译： 用于实现用于确定性地处理所选数据的多级系统模型的方法包括响应于来自同步时钟的周期开始信号，调用同步调度器以在电子设备上选择，调度和执行主动同步过程的picokernel模块。 活动同步过程可以选择性地设置plesiochron标志，从而将相应的plesiochron过程指定为活动的准同步过程。 一旦在给定的等时循环中已经执行所有活动的同步过程，则picokernel可以调用一个同步调度器来选择，调度和执行电子设备上的任何活动的同步过程。

公开(公告)号：US06578109B1

公开(公告)日：2003-06-10

申请号：US09606813

申请日：2000-06-29

申请人： Glen D. Stone ,  Scott D. Smyers ,  Bruce A. Fairman

发明人： Glen D. Stone ,  Scott D. Smyers ,  Bruce A. Fairman

IPC分类号： G06F1200

CPC分类号： G06F12/0842 ,  G06F12/121

摘要： A system and method for effectively implementing isochronous processor cache comprises a memory device for storing high-priority isochronous information, an isochronous cache coupled to the memory device for locally caching the isochronous information from the memory device, and a processor device for accessing and utilizing the isochronous information that is stored in the isochronous cache. The isochronous cache is reserved for storing the isochronous information, and may be reconfigured into a selectable number of cache channels of varying size that each corresponds to an associated isochronous process.

公开(公告)号：US06934781B2

公开(公告)日：2005-08-23

申请号：US10226025

申请日：2002-08-22

申请人： Glen D. Stone ,  Bruce A. Fairman ,  Scott D. Smyers

发明人： Glen D. Stone ,  Bruce A. Fairman ,  Scott D. Smyers

IPC分类号： G06F13/362 ,  G06F13/364 ,  H04L12/40 ,  H04L12/403 ,  H04L12/64

CPC分类号： H04L12/40058 ,  G06F13/364

摘要： A system and method for effectively performing isochronous data transfers comprises a network device including an input/output (I/O) bus that is coupled to an input/output (I/O) node and an isochronous-capable network interface. The network interface and the I/O node may send requests to an arbiter for control of the I/O bus to perform a data transfer operation. In accordance with the present invention, an arbiter filter is interposed between the arbiter and both the network interface and the I/O node to filter respective requests for control of the I/O bus. The network interface advantageously provides an isochronous request to the arbiter filter to thereby de-assert conflicting requests so that the network interface may effectively perform a time-sensitive isochronous data transfer.

摘要翻译： 用于有效执行等时数据传输的系统和方法包括网络设备，其包括耦合到输入/输出（I / O）节点和等时同步网络接口的输入/输出（I / O）总线。 网络接口和I / O节点可以向仲裁器发送请求以控制I / O总线以执行数据传输操作。 根据本发明，在仲裁器和网络接口和I / O节点之间插入一个仲裁器滤波器，以过滤各个I / O总线控制请求。 网络接口有利地向仲裁器过滤器提供同步请求，从而解除冲突请求，使得网络接口可以有效地执行时间敏感的等时数据传输。

公开(公告)号：US06728834B2

公开(公告)日：2004-04-27

申请号：US10352260

申请日：2003-01-27

申请人： Glen D. Stone ,  Scott D. Smyers ,  Bruce A. Fairman

发明人： Glen D. Stone ,  Scott D. Smyers ,  Bruce A. Fairman

IPC分类号： G06F1200

CPC分类号： G06F12/0842 ,  G06F12/121

摘要： A system and method for effectively implementing isochronous processor cache comprises a memory device for storing high-priority isochronous information, an isochronous cache coupled to the memory device for locally caching the isochronous information from the memory device, and a processor device for accessing and utilizing the isochronous information that is stored in the isochronous cache. The isochronous cache is reserved for storing the isochronous information, and may be reconfigured into a selectable number of cache channels of varying size that each corresponds to an associated isochronous process.

摘要翻译： 用于有效实现等时处理器高速缓存的系统和方法包括用于存储高优先级等时信息的存储器设备，耦合到存储器设备的用于本地缓存来自存储器设备的等时信息的同步高速缓存器，以及用于访问和利用 存储在同步缓存中的同步信息。 保留同步缓存用于存储等时信息，并且可以将其重配置为可选数量的不同大小的高速缓存信道，每个高速缓存信道对应于相关联的等时进程。

公开(公告)号：US06557067B1

公开(公告)日：2003-04-29

申请号：US09497322

申请日：2000-02-03

申请人： David V. James ,  Scott D. Smyers ,  Glen D. Stone ,  Bruce A. Fairman

发明人： David V. James ,  Scott D. Smyers ,  Glen D. Stone ,  Bruce A. Fairman

IPC分类号： G06F1336

CPC分类号： H04L12/56

摘要： A system and method to effectively compensate for delays in an electronic interconnect comprises a controller that initially schedules a first transmission from a first talker device to several listener devices. The controller then schedules a second talker device to pre-roll a second transmission and selectively routes the second transmission to compensate for delays introduced by components of said electronic interconnect to thereby provide a seamless transmission stream to the several listeners.

摘要翻译： 有效地补偿电子互连中的延迟的系统和方法包括控制器，其最初调度从第一讲话器设备到多个收听器设备的第一传输。 然后，控制器调度第二讲话器设备来预先滚动第二传输，并且选择性地路由第二传输以补偿由所述电子互连的组件引入的延迟，从而向多个收听者提供无缝传输流。

公开(公告)号：US06463489B1

公开(公告)日：2002-10-08

申请号：US09383490

申请日：1999-08-26

申请人： Glen D. Stone ,  Bruce A. Fairman ,  Scott D. Smyers

发明人： Glen D. Stone ,  Bruce A. Fairman ,  Scott D. Smyers

IPC分类号： G06F1300

CPC分类号： H04L12/40058 ,  G06F13/364

摘要： A system and method for effectively performing isochronous data transfers comprises a network device including an input/output (I/O) bus that is coupled to an input/output (I/O) node and an isochronous-capable network interface. The network interface and the I/O node may send requests to an arbiter for control of the I/O bus to perform a data transfer operation. In accordance with the present invention, an arbiter filter is interposed between the arbiter and both the network interface and the I/O node to filter respective requests for control of the I/O bus. The network interface advantageously provides an isochronous request to the arbiter filter to thereby de-assert conflicting requests so that the network interface may effectively perform a time-sensitive isochronous data transfer.

摘要翻译： 用于有效执行等时数据传输的系统和方法包括网络设备，其包括耦合到输入/输出（I / O）节点和等时同步网络接口的输入/输出（I / O）总线。 网络接口和I / O节点可以向仲裁器发送请求以控制I / O总线以执行数据传输操作。 根据本发明，在仲裁器和网络接口和I / O节点之间插入一个仲裁器滤波器，以过滤各个I / O总线控制请求。 网络接口有利地向仲裁器过滤器提供同步请求，从而解除冲突请求，使得网络接口可以有效地执行时间敏感的等时数据传输。

公开(公告)号：US06847650B1

公开(公告)日：2005-01-25

申请号：US09607066

申请日：2000-06-29

申请人： Glen D. Stone ,  David V. James ,  Bruce A. Fairman

发明人： Glen D. Stone ,  David V. James ,  Bruce A. Fairman

IPC分类号： G06F12/00 ,  H04L12/28 ,  H04L12/40 ,  H04L12/64

CPC分类号： H04L12/40058 ,  H04L12/40117 ,  H04L12/6418

摘要： A system and method for utilizing a memory device to support isochronous processes comprises a memory device that may be partitioned to provide an isochronous memory for storing high-priority isochronous information, and a processor device for accessing and utilizing the isochronous information that is stored in the isochronous memory. The isochronous memory is reserved for storing the isochronous information, and may be reconfigured into a selectable number of memory channels of varying size that each corresponds to an associated isochronous process.

摘要翻译： 一种利用存储器件来支持同步过程的系统和方法包括可被分区以提供用于存储高优先级等时信息的同步存储器的存储器设备，以及用于访问和利用存储在该等时信息中的等时信息的处理器设备 同步存储器 保留同步存储器用于存储同步信息，并且可以将其重新配置为可选数量的不同大小的存储器通道，每个存储器通道对应于相关联的同步过程。

公开(公告)号：US6167471A

公开(公告)日：2000-12-26

申请号：US172994

申请日：1998-10-14

申请人： Jung-Jen Liu ,  Bruce A. Fairman

发明人： Jung-Jen Liu ,  Bruce A. Fairman

IPC分类号： G06F13/12 ,  H04L12/28 ,  H04L12/56 ,  G06F13/10 ,  G06F9/30 ,  G11C8/00 ,  H04J3/26

CPC分类号： H04L49/90

摘要： An apparatus for dispatching a processing element to a program location based on a channel number of received data includes a channel pointer register having a number of storage locations each with a channel number field, a valid bit field and a corresponding instruction pointer field. When an isochronous channel is allocated for use for reception, the host device programs the channel number and a corresponding instruction pointer value into a storage location. When a storage location is programmed, a valid bit within that storage location is also preferably set. The corresponding instruction pointer value points to a series of instructions which are to be used to process data received on that isochronous channel. When isochronous data is then received, the channel number on which the data is received is compared to the channel numbers within the valid storage locations in the channel pointer register. If one of the channel numbers within a valid storage location matches the channel number of the received data, then the corresponding instruction pointer value is output and the data is processed according to a series of instructions beginning at the location specified by the corresponding instruction pointer value. Otherwise, if the channel number of the received data does not match any of the channel numbers within valid storage locations then a default instruction pointer value is output and the received data is processed according to a series of instructions beginning at the location specified by the default instruction pointer value.

摘要翻译： 一种用于基于接收数据的频道号将处理元件分配到节目位置的装置包括具有多个存储位置的频道指针寄存器，每个存储位置具有频道号字段，有效位字段和相应的指令指针字段。 当同步信道被分配用于接收时，主机设备将信道号和相应的指令指针值编程到存储位置。 当存储位置被编程时，也优选地设置该存储位置内的有效位。 相应的指令指针值指向要用于处理在同步信道上接收的数据的一系列指令。 当接收到等时数据时，将接收数据的通道号与通道指针寄存器中的有效存储位置内的通道号进行比较。 如果有效存储位置中的一个通道号与接收到的数据的通道号匹配，则输出相应的指令指针值，并根据从相应指令指针值指定的位置开始的一系列指令来处理数据 。 否则，如果接收到的数据的通道号与有效存储位置内的任何通道号不匹配，则输出默认指令指针值，并根据从默认值指定的位置开始的一系列指令来处理接收到的数据 指令指针值。