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1.发明授权公开(公告)号：US06453376B1
公开(公告)日：2002-09-17
申请号：US09521334
申请日：2000-03-09
IPC分类号： G06F1200
CPC分类号： G06F9/485 , G06F9/4881 , G06F2209/485
摘要： A method for implementing scheduling mechanisms with selectable resource modes comprises at least one resource characterization set that includes a plurality of resource characterizations that each have resource requirements for executing a requested process. The plurality of resource characterizations may include a most mode, a best mode, and a worst mode. An allocation manager may then select a resource mode, and compare the corresponding resource requirements for the requested process to the currently-available device resources. The allocation manager may then authorize or deny the requested process depending upon whether the currently-available resources are sufficient to adequately service the resource requirements of the requested process.
摘要翻译： 用于用可选资源模式实现调度机制的方法包括至少一个资源表征集合，其包括多个资源表征，每个资源表征都具有用于执行所请求的进程的资源需求。 多个资源表征可以包括大多数模式，最佳模式和最差模式。 然后，分配管理器可以选择资源模式，并将所请求进程的相应资源需求与当前可用的设备资源进行比较。 然后，分配管理器可以根据当前可用的资源是否足以充分地满足所请求进程的资源需求来授权或拒绝所请求的进程。
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2.发明授权Method for utilizing resource characterizations to optimize performance in an electronic device 有权利用资源表征来优化电子设备中的性能的方法公开(公告)号：US06973653B1
公开(公告)日：2005-12-06
申请号：US09521308
申请日：2000-03-09
CPC分类号： G06F9/485 , G06F9/4881 , G06F2209/485
摘要： A method for providing optimal performance in an electronic device comprises at least one resource characterization that includes resource requirements for executing a requested process. An allocation manager may then compare the resource requirements for the requested process to the currently-available device resources. The allocation manager may then authorize or deny the requested process depending upon whether the currently-available resources are sufficient to adequately service the resource requirements of the requested process.
摘要翻译： 用于在电子设备中提供最佳性能的方法包括至少一种资源表征，其包括用于执行所请求的过程的资源需求。 然后，分配管理器可以将所请求进程的资源需求与当前可用的设备资源进行比较。 然后，分配管理器可以根据当前可用的资源是否足以充分地满足所请求进程的资源需求来授权或拒绝所请求的进程。
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3.发明授权Method for implementing a multi-level system model for deterministically handling selected data 有权用于实现用于确定性地处理所选数据的多级系统模型的方法公开(公告)号：US06952826B1
公开(公告)日：2005-10-04
申请号：US09691879
申请日：2000-10-18
CPC分类号： G06F9/4881
摘要： A method for implementing a multi-level system model for deterministically handling selected data comprises a picokernel module that invokes an isochronous scheduler to select, schedule, and execute active isochronous processes on an electronic device in response to a cycle start signal from an isochronous clock. The active isochronous processes may selectively set plesiochronous flags to thereby designate corresponding plesiochronous processes as active plesiochronous processes. Once all active isochronous processes have been executed in a given isochronous cycle, then the picokernel may invoke a plesiochronous scheduler to select, schedule, and execute any active plesiochronous processes on the electronic device.
摘要翻译： 用于实现用于确定性地处理所选数据的多级系统模型的方法包括响应于来自同步时钟的周期开始信号，调用同步调度器以在电子设备上选择，调度和执行主动同步过程的picokernel模块。 活动同步过程可以选择性地设置plesiochron标志，从而将相应的plesiochron过程指定为活动的准同步过程。 一旦在给定的等时循环中已经执行所有活动的同步过程，则picokernel可以调用一个同步调度器来选择，调度和执行电子设备上的任何活动的同步过程。
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公开(公告)号：US06578109B1
公开(公告)日：2003-06-10
申请号：US09606813
申请日：2000-06-29
申请人： Glen D. Stone , Scott D. Smyers , Bruce A. Fairman
发明人： Glen D. Stone , Scott D. Smyers , Bruce A. Fairman
IPC分类号： G06F1200
CPC分类号： G06F12/0842 , G06F12/121
摘要： A system and method for effectively implementing isochronous processor cache comprises a memory device for storing high-priority isochronous information, an isochronous cache coupled to the memory device for locally caching the isochronous information from the memory device, and a processor device for accessing and utilizing the isochronous information that is stored in the isochronous cache. The isochronous cache is reserved for storing the isochronous information, and may be reconfigured into a selectable number of cache channels of varying size that each corresponds to an associated isochronous process.
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5.发明授权公开(公告)号：US06934781B2
公开(公告)日：2005-08-23
申请号：US10226025
申请日：2002-08-22
申请人： Glen D. Stone , Bruce A. Fairman , Scott D. Smyers
发明人： Glen D. Stone , Bruce A. Fairman , Scott D. Smyers
IPC分类号： G06F13/362 , G06F13/364 , H04L12/40 , H04L12/403 , H04L12/64
CPC分类号： H04L12/40058 , G06F13/364
摘要： A system and method for effectively performing isochronous data transfers comprises a network device including an input/output (I/O) bus that is coupled to an input/output (I/O) node and an isochronous-capable network interface. The network interface and the I/O node may send requests to an arbiter for control of the I/O bus to perform a data transfer operation. In accordance with the present invention, an arbiter filter is interposed between the arbiter and both the network interface and the I/O node to filter respective requests for control of the I/O bus. The network interface advantageously provides an isochronous request to the arbiter filter to thereby de-assert conflicting requests so that the network interface may effectively perform a time-sensitive isochronous data transfer.
摘要翻译： 用于有效执行等时数据传输的系统和方法包括网络设备，其包括耦合到输入/输出（I / O）节点和等时同步网络接口的输入/输出（I / O）总线。 网络接口和I / O节点可以向仲裁器发送请求以控制I / O总线以执行数据传输操作。 根据本发明，在仲裁器和网络接口和I / O节点之间插入一个仲裁器滤波器，以过滤各个I / O总线控制请求。 网络接口有利地向仲裁器过滤器提供同步请求，从而解除冲突请求，使得网络接口可以有效地执行时间敏感的等时数据传输。
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6.发明授权公开(公告)号：US06728834B2
公开(公告)日：2004-04-27
申请号：US10352260
申请日：2003-01-27
申请人： Glen D. Stone , Scott D. Smyers , Bruce A. Fairman
发明人： Glen D. Stone , Scott D. Smyers , Bruce A. Fairman
IPC分类号： G06F1200
CPC分类号： G06F12/0842 , G06F12/121
摘要： A system and method for effectively implementing isochronous processor cache comprises a memory device for storing high-priority isochronous information, an isochronous cache coupled to the memory device for locally caching the isochronous information from the memory device, and a processor device for accessing and utilizing the isochronous information that is stored in the isochronous cache. The isochronous cache is reserved for storing the isochronous information, and may be reconfigured into a selectable number of cache channels of varying size that each corresponds to an associated isochronous process.
摘要翻译： 用于有效实现等时处理器高速缓存的系统和方法包括用于存储高优先级等时信息的存储器设备，耦合到存储器设备的用于本地缓存来自存储器设备的等时信息的同步高速缓存器，以及用于访问和利用 存储在同步缓存中的同步信息。 保留同步缓存用于存储等时信息，并且可以将其重配置为可选数量的不同大小的高速缓存信道，每个高速缓存信道对应于相关联的等时进程。
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7.发明授权System and method to effectively compensate for delays in an electronic interconnect 失效系统和方法有效补偿电子互连中的延迟公开(公告)号：US06557067B1
公开(公告)日：2003-04-29
申请号：US09497322
申请日：2000-02-03
IPC分类号： G06F1336
CPC分类号： H04L12/56
摘要： A system and method to effectively compensate for delays in an electronic interconnect comprises a controller that initially schedules a first transmission from a first talker device to several listener devices. The controller then schedules a second talker device to pre-roll a second transmission and selectively routes the second transmission to compensate for delays introduced by components of said electronic interconnect to thereby provide a seamless transmission stream to the several listeners.
摘要翻译： 有效地补偿电子互连中的延迟的系统和方法包括控制器，其最初调度从第一讲话器设备到多个收听器设备的第一传输。 然后，控制器调度第二讲话器设备来预先滚动第二传输，并且选择性地路由第二传输以补偿由所述电子互连的组件引入的延迟，从而向多个收听者提供无缝传输流。
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8.发明授权公开(公告)号：US06463489B1
公开(公告)日：2002-10-08
申请号：US09383490
申请日：1999-08-26
申请人： Glen D. Stone , Bruce A. Fairman , Scott D. Smyers
发明人： Glen D. Stone , Bruce A. Fairman , Scott D. Smyers
IPC分类号： G06F1300
CPC分类号： H04L12/40058 , G06F13/364
摘要： A system and method for effectively performing isochronous data transfers comprises a network device including an input/output (I/O) bus that is coupled to an input/output (I/O) node and an isochronous-capable network interface. The network interface and the I/O node may send requests to an arbiter for control of the I/O bus to perform a data transfer operation. In accordance with the present invention, an arbiter filter is interposed between the arbiter and both the network interface and the I/O node to filter respective requests for control of the I/O bus. The network interface advantageously provides an isochronous request to the arbiter filter to thereby de-assert conflicting requests so that the network interface may effectively perform a time-sensitive isochronous data transfer.
摘要翻译： 用于有效执行等时数据传输的系统和方法包括网络设备，其包括耦合到输入/输出（I / O）节点和等时同步网络接口的输入/输出（I / O）总线。 网络接口和I / O节点可以向仲裁器发送请求以控制I / O总线以执行数据传输操作。 根据本发明，在仲裁器和网络接口和I / O节点之间插入一个仲裁器滤波器，以过滤各个I / O总线控制请求。 网络接口有利地向仲裁器过滤器提供同步请求，从而解除冲突请求，使得网络接口可以有效地执行时间敏感的等时数据传输。
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9.发明授权Method for utilizing concurrent context switching to support isochronous processes 有权利用并行上下文切换支持同步进程的方法公开(公告)号：US07318090B1
公开(公告)日：2008-01-08
申请号：US09661226
申请日：2000-09-13
申请人： Bruce A Fairman , Glen D. Stone , Scott D. Smyers
发明人： Bruce A Fairman , Glen D. Stone , Scott D. Smyers
IPC分类号： G06F15/173 , G06F3/00 , G06F9/46
CPC分类号： G06F9/462
摘要： A method for utilizing concurrent context switching to support isochronous processes preferably comprises a main context that is configured to support system execution tasks, a first concurrent context that supports a first set of concurrent execution and loading procedures, and a second concurrent context that supports a second set of concurrent execution and loading procedures. A context control module preferably manages switching and loading procedures between the main context, the first concurrent context, and the second concurrent context. The context control module may perform successive concurrent context switching procedures by alternating between the first concurrent context and the second concurrent context to thereby sequentially support any desired number of isochronous processes.
摘要翻译： 一种利用并行上下文切换来支持同步进程的方法优选地包括被配置为支持系统执行任务的主上下文，支持第一组并行执行和加载过程的第一并发上下文以及支持第二并发上下文的第二并发上下文 一组并发执行和加载过程。 上下文控制模块优选地管理主上下文，第一并发上下文和第二并发上下文之间的切换和加载过程。 上下文控制模块可以通过在第一并发上下文和第二并发上下文之间交替来执行连续的并行上下文切换过程，从而顺序地支持任何期望数量的等时进程。
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10.发明授权Asynchronous data pipe for automatically managing asynchronous data transfers between an application and a bus structure 有权用于在应用程序和总线结构之间自动管理异步数据传输的异步数据管道公开(公告)号：US07944952B2
公开(公告)日：2011-05-17
申请号：US12488338
申请日：2009-06-19
申请人： Scott D. Smyers
发明人： Scott D. Smyers
IPC分类号： H04J1/16
CPC分类号： H04L12/6418 , G06F13/128 , H04L12/40071
摘要： An asynchronous data pipe (ADP) automatically generates transactions necessary to complete asynchronous data transfer operations for an application over a bus structure. The ADP includes a register file which is programmed and initiated by the application. The register file includes the bus speed, transaction label, transaction code, destination node identifier, destination offset address, length of each data packet, packet counter, packet counter bump field, control field and a status field. During a data transfer operation, the ADP generates the transactions necessary to complete the operation over the appropriate range of addresses, using the information in the register file as a template. The ADP increments the value in the destination offset address field for each transaction according to the length of each data packet, unless the incrementing feature has been disabled and the transactions are to take place at a fixed address. The packet counter represents the number of transactions remaining to be generated. The packet counter value is decremented after each packet of data is transferred. The application can increment the packet counter value by writing to the packet counter bump field. A multiplexer is included within a system having multiple ADPs for multiplexing the information from the ADPs onto the bus structure. A demultiplexer is included within a system having multiple ADPs for routing information from the bus structure to the appropriate ADP.
摘要翻译： 异步数据管道（ADP）自动生成通过总线结构为应用程序完成异步数据传输操作所需的事务。 ADP包括由应用程序编程和启动的寄存器文件。 寄存器文件包括总线速度，事务标签，事务代码，目标节点标识符，目的地偏移地址，每个数据包的长度，数据包计数器，数据包计数器突发字段，控制字段和状态字段。 在数据传输操作期间，ADP使用寄存器文件中的信息作为模板，生成在适当的地址范围内完成操作所需的交易。 ADP根据每个数据包的长度，增加每个事务的目的地偏移地址字段中的值，除非增量功能被禁用，并且事务将在固定地址进行。 分组计数器表示剩余的要生成的事务数。 每个数据包传输后，分组计数器值递减。 应用程序可以通过写入数据包计数器凸块字段来增加数据包计数器值。 多路复用器包括在具有多个ADP的系统中，用于将来自ADP的信息复用到总线结构上。 解复用器被包括在具有多个ADP的系统中，用于将信息从总线结构路由到适当的ADP。
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